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Multidimensional analog test metrics estimation using extreme value theory and statistical blockade

Published:29 May 2013Publication History

ABSTRACT

The high cost of testing certain analog, mixed-signal, and RF circuits has driven in the recent years the development of alternative low-cost tests to replace the most costly or even all standard specification tests. However, there is a lack of solutions for evaluating the parametric test error, that is, the test error for circuits with process variations, resulting from this replacement. For this reason, test engineers are often reluctant to adopt alternative tests since it is not guaranteed that test cost reduction is not achieved at the expense of sacrificing test quality. In this paper, we present a technique to estimate the parametric test error fast and reliably with parts per million accuracy. The technique is based on extreme value theory and statistical blockade. Relying on a small number of targeted simulations, it is capable of providing accurate estimates of parametric test error in the general scenario where a set of alternative tests replaces all or a subset of standard specification tests.

References

  1. D. Mannath, D. Webster, V. Montano-Martinez, D. Cohen, S. Kush, T. Ganesan, and A. Sontakke, "Structural approach for built-in tests in RF devices," in Proc. IEEE International Test Conference, 2010, Paper 14.1.Google ScholarGoogle Scholar
  2. L. Abdallah, H.-G. Stratigopoulos, S. Mir, and C. Kelma, "Experiences with non-intrusive sensors for RF built-in test" in Proc. IEEE International Test Conference, 2012, Paper 17.1. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. S. Biswas, P. Li, R. D. (Shawn) Blanton, and L. Pileggi, "Specification test compaction for analog circuits and MEMS," in Proc. Design, Automation & Test in Europe Conference, 2005, pp. 164--169. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. H.-G. Stratigopoulos, P. Drineas, M. Slamani, and Y. Makris, "RF specification test compaction using learning machines," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 6, pp. 998--1002, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. S. Sunter and N. Nagi, "Test metrics for analog parametric faults," in Proc. IEEE VLSI Test Symposium, 1999, pp. 226--34. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. P. Embrechts, C. Klüppelberg, and T. Mikosch, Modelling Extremal Events for Insurance and Finance, Stochastic Modeling and Applied Probability. Springer, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. S. Coles, An Introduction to Statistical Modeling of Extreme Values, Springer Series in Statistics. Springer, 2001.Google ScholarGoogle Scholar
  8. A. Singhee, J. Wang, B. H. Calhoun, and R. A. Rutenbar, "Recursive statistical blockade: An enhanced technique for rare event simulation with application to SRAM circuit design," in Proc. IEEE International Conference on VLSI Design, 2008, pp. 131--136. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. A. Singhee and R. A. Rutenbar, "Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1176--1189, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. D. E. Hocevar, M. R. Lightner, and T. N. Trick, "A study of variance reduction techniques for estimating circuit yields," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, no. 3, pp. 180--192, 1983. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. L. Milor and A. L. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 6, pp. 796--813, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. E. Yilmaz and S. Ozev, "Fast and accurate DPPM computation using model based filtering," in Proc. IEEE European Test Symposium, 2011, pp. 165--170. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. A. Bounceur, S. Mir, E. Simeu, and L. Rolindez, "Estimation of test metrics for the optimisation of analogue circuit testing," Journal of Electronic Testing: Theory and Applications, vol. 23, no. 6, pp. 471--484, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. A. Bounceur, S. Mir, and H.-G. Stratigopoulos, "Estimation of analog parametric test metrics using copulas," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 9, pp. 1400--1410, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. H.-G. Stratigopoulos, S. Mir, and A. Bounceur, "Evaluation of analog/RF test measurements at the design stage," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 582--590, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. N. Kupp, H.-G. Stratigopoulos, Y. Makris, and P. Drineas, "On proving the efficiency of alternative RF tests," in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2011, pp. 762--767. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. H.-G. Stratigopoulos, "Test metrics model for analog test development," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1116--1128, 2012.Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Y. Courant, P. Hérédia, and F. Mohamed, "Nonlinear modelling for sub 65nm IC statistical analysis," in 2nd European Workshop on CMOS Variability, 2011.Google ScholarGoogle Scholar

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            cover image ACM Conferences
            DAC '13: Proceedings of the 50th Annual Design Automation Conference
            May 2013
            1285 pages
            ISBN:9781450320719
            DOI:10.1145/2463209

            Copyright © 2013 ACM

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            Publication History

            • Published: 29 May 2013

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