A survey on cache tuning from a power/energy perspective

Abstract

Low power and/or energy consumption is a requirement not only in embedded systems that run on batteries or have limited cooling capabilities, but also in desktop and mainframes where chips require costly cooling techniques. Since the cache subsystem is typically the most power/energy-consuming subsystem, caches are good candidates for power/energy optimizations, and therefore, cache tuning techniques are widely researched. This survey focuses on state-of-the-art offline static and online dynamic cache tuning techniques and summarizes the techniques' attributes, major challenges, and potential research trends to inspire novel ideas and future research avenues.

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Index Terms

• General and reference

  • Document types

    • Surveys and overviews

• Hardware

  • Hardware validation

  • Integrated circuits

    • Semiconductor memory

      • Dynamic memory