research-article

Multi-port FinFET SRAM design

Authors:

Kartik MohanramAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 293 - 298

https://doi.org/10.1145/2483028.2483113

Published: 02 May 2013 Publication History

Abstract

Multi-port SRAMs are essential for caches and shared data structures, especially in modern multi-core SoCs. The FinFET device, which offers high threshold voltage and high on/off current ratio, is a promising candidate for multi-port SRAMs for fast read/write speed, high cell density, and low power consumption. In this paper, we perform the first study of multi-port FinFET SRAMs, including the double-ended multi-port FinFET SRAM and three single-ended multi-port FinFET SRAMs with isolated read ports. We evaluate the static noise margin, leakage current, and read/write performance of these structures with the predictive technology model for FinFETs. Our results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over the double-ended structure at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended structures can achieve equivalent write performance to the double-ended structure for 9% area overhead.

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Cited By

Li JMohanram K(2017)Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.13(47-52)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.13
Gopireddy BSong CTorrellas JKim NAgrawal AMishra A(2016)ScalCore: Designing a core for voltage scalability2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446104(681-693)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446104
Pasandi GFakhraie S(2015)A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read OperationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.237751823:11(2438-2446)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2377518
Show More Cited By

Index Terms

Multi-port FinFET SRAM design
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Static memory

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Published In

cover image ACM Conferences

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 May 2013

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GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Li JMohanram K(2017)Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.13(47-52)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.13
Gopireddy BSong CTorrellas JKim NAgrawal AMishra A(2016)ScalCore: Designing a core for voltage scalability2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446104(681-693)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446104
Pasandi GFakhraie S(2015)A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read OperationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.237751823:11(2438-2446)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2377518
Pasandi GQasemi EFakhraie S(2014)A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology2014 22nd Iranian Conference on Electrical Engineering (ICEE)10.1109/IranianCEE.2014.6999569(382-386)Online publication date: May-2014
https://doi.org/10.1109/IranianCEE.2014.6999569
Pasandi GFakhraie S(2014)A new VDD- and GND-floating rails SRAM with improved read SNM and without multi-level voltage regulator2014 22nd Iranian Conference on Electrical Engineering (ICEE)10.1109/IranianCEE.2014.6999568(377-381)Online publication date: May-2014
https://doi.org/10.1109/IranianCEE.2014.6999568

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