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Timing-constrained replacement using spare cells for design changes

Published:02 May 2013Publication History

ABSTRACT

Spare cells have been widely used to realize design changes at post-placement stage for functional changes or timing violations. However, many prior works relative to spare cell utilization neglect the timing effect due to spare cell rewiring. In this paper, the problem of timing-constrained cell replacement using spare cells is firstly formulated to consider the timing effect of the rewiring result. Furthermore, a three-phase approach is proposed to replace the changed cells in a combinational circuit with available spare cells while the timing constraints on the changed cells are satisfied. Experimental results show that our approach can efficiently realize the functional changes under the timing constraints for 5 tested cases.

References

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      • Published in

        cover image ACM Conferences
        GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
        May 2013
        368 pages
        ISBN:9781450320320
        DOI:10.1145/2483028

        Copyright © 2013 Authors

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 2 May 2013

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        GLSVLSI '13 Paper Acceptance Rate76of238submissions,32%Overall Acceptance Rate312of1,156submissions,27%

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