skip to main content
10.1145/2500727.2500743acmotherconferencesArticle/Chapter ViewAbstractPublication PagesapsysConference Proceedingsconference-collections
research-article

A read-disturb management technique for high-density NAND flash memory

Published:29 July 2013Publication History

ABSTRACT

The read-disturb problem is emerging as one of the main reliability issues for future high-density NAND flash memory. A read-disturb error, which causes data loss, occurs to data in a page when a large number of reads are performed to its neighboring pages in the same block. In this paper, we propose a novel read-disturb management technique which reduces the frequency of expensive data migrations needed for avoiding read-disturb errors. Our technique proactively converts highly skewed read accesses to a small number of blocks into more balanced read accesses to a large number of blocks by intelligently changing data block locations accessed. Our experimental results show that our technique is effective in handling the read-disturb problem, reducing the time overhead of data migrations on average by 50% over an FTL based on the existing read-disturb management technique.

References

  1. http://iotta.snia.org/traces/158.Google ScholarGoogle Scholar
  2. http://traces.cs.umass.edu/index.php/Storage/Storage.Google ScholarGoogle Scholar
  3. A. A. Chien et al. Moore's Law: The First Ending and A New Beginning. Tech. rep., 2012.Google ScholarGoogle Scholar
  4. D. Narayanan et al. Write Off-Loading: Practical Power Management for Enterprise Storage. ACM Transactions on Storage 4, 3 (2008), 1--23. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. H. H. Frost et al. Efficient Reduction of Read Disturb Errors in NAND Flash Memory, 2010. US Patent 7,818,525.Google ScholarGoogle Scholar
  6. J. Zhang et al. Synthesizing Representative I/O Workloads for TPC-H. In Proc. of the International Symposium on High Performance Computer Architecture (2004). Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. M. Kang et al. Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories. Japanese Journal of Applied Physics 48, 4 (2009), 04C062-1-04C062-6.Google ScholarGoogle ScholarCross RefCross Ref
  8. S. H. Shin et al. A New 3-bit Programming Algorithm Using SLC-to-TLC Migration for 8MB/s High Performance TLC NAND Flash Memory. In Proc. of the IEEE Symposium on VLSI Circuits (2012).Google ScholarGoogle ScholarCross RefCross Ref

Recommendations

Comments

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Sign in
  • Published in

    cover image ACM Other conferences
    APSys '13: Proceedings of the 4th Asia-Pacific Workshop on Systems
    July 2013
    131 pages
    ISBN:9781450323161
    DOI:10.1145/2500727

    Copyright © 2013 ACM

    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 29 July 2013

    Permissions

    Request permissions about this article.

    Request Permissions

    Check for updates

    Qualifiers

    • research-article

    Acceptance Rates

    APSys '13 Paper Acceptance Rate23of73submissions,32%Overall Acceptance Rate149of386submissions,39%

PDF Format

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader