Barton J. Sano
- Bakoglu90.H. Bakoglu and T. Whiteside, "RISC System/ 6000 Hardware Overview," IBM RISC System Technology, 1990. Google Scholar
Digital Library
- Case91.Brian Case, "Superscalar Techniques: SuperSPARC vs. 88110," Microprocessor Report, Vol. 5, No. 22, Dec 4th, 1991.Google Scholar
- Case93.Brian Case, "Intel Reveals Pentium Implementation," Microprocessor Report, Vol. 7, No. 4, March 29th, 1993.Google Scholar
- Chang91.P. Chang, S. Mahlke, W. Chen, N. Warter, and W. Hwu, "IMPACT: An Architectural Framework for Multi- Instruction-Issue Processors," Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991 Google ScholarDigital Library
- Cohn89.Robert Cohn, et al., "Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor," The Third Conference on Architectural Support for Programming Languages and Operating Systems, April 1989. Google ScholarDigital Library
- Colwell87.R. P. Colwell et al., "A VLIW Architecture for a Trace Scheduling Compiler," Second International Conference on Architectural Support for Programming Languages and Operating Systems, October 1987. Google ScholarCross Ref
- Dobb92.Danial W. Dobberpuhl, et al., "A 200 MHz 64-b Dual-Issue CMOS Microprocessor," IEEE Journal of Solid- State Circuits, Vol. 27, No. 11, Nov. 1992.Google ScholarCross Ref
- Fisher81.Joseph A. Fisher, '~rrace Scheduling: A Technique for Global Microcode Compaction," IEEE Transactions on Computers, Vol. C-30, NO. 7, July 1981.Google Scholar
- Fisher83.Joseph A. Fisher, "Very Long Instruction Word Architectures and the ELI-512," Proceedings of the l Oth Annual international Symposium on Computer Architecture, June 1983. Google ScholarDigital Library
- Fisher91.Joseph A. Fisher and B. Ramakrishna Rau, "Instruction-Level Parallel Processing," Science, Sept. 13th, 1991.Google Scholar
- Flynn72.Michael J. Flynn, "Some Computer Organization and Their Effectiveness," IEEE Trans. on Computer, vol. c-21, no. 9, Sept. 1972.Google ScholarDigital Library
- Forsyth91.Richard Forsyth, Bob K~siak, and Roger Shopexd, '~T9(X)0 - Superscalar Transputer," Hot Chips III Presentation, Aug 1991.Google Scholar
- Goodman85.J.R. Goodman et al., "PIPE:A VLSI Decoupled Architecture," Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985. Google ScholarDigital Library
- Gwen91.Linley Gwennap, "Motorola Details Plan to Extend 68K Line," Microprocessor Report, Vol. 6, No. 15, Nov 18 th, 1992.Google Scholar
- Horst90.R.W. Horst, R.L. Harris, and R.L.Jardine, "Multiple Instruction Issue in the NonStop Cyclone Processor," Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990. Google ScholarDigital Library
- Intel860."64-Bit Microprocessor Programmers Reference Manual," Intel Corporation, Mt Prospect IL, 1990. Google ScholarDigital Library
- Intel960."80960CA User's Manual," Intel Corporation, Santa Clara CA, 1989.Google Scholar
- Jaffe92.William Jaffe, Bob Miller, and Jeff Yetter "A 200 MFLOP Precision Architecture Processor," Hot Chips IV Presentation, Aug 1992.Google Scholar
- JSmith89.J.E. Smith, "Dynamic Insuuction Scheduling and the Astronautics ZS-i," IEEE Computer, pp. 21-35, June 1989. Google ScholarDigital Library
- Jouppi91.Norman P. Jouppi and David W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpiplined Machines," The Third Conference on Architectural Support for Programming Languages and Operating Systems, April 1989. Google ScholarDigital Library
- Knieser92.M. Knieser and C. Papachristou, "Y-Pipe: A Conditional Branching Scheme Without Pipeline Delays," The 25th Annual International Symposium on Microarchitecture, December 1992. Google ScholarDigital Library
- Kuga91.M. Kuga, K. Murakami, and S. Tomita, "DSNS (Dynamically -hazard-resolved, Statically -code-scheduled, Nonuniform Superscalar): Yet Another Superscalar Processor Architecture," Computer Architecture News, vol. 19, no. 4, June 1991. Google ScholarDigital Library
- Lam88.Monica Lain, "Software Pipelining: An Effective Scheduling Technique for VLIW Machines," ACM SIGPLAN '88 Conference on Programming Language Design and Implementation, 1988. Google ScholarDigital Library
- Lam92.M0nica Lain and Robert P. Wilson, "Limits of Control FLow on Parallelism," Proceedings of the 19th Annual International Symposium on Computer Architecture, June 1992. Google ScholarDigital Library
- Marko91.Reuven Marko and Motti Beck, "National's Swordfish A Superscalar with DSP," Hot Chips III Presentation, Aug 1991.Google Scholar
- MSmith90.M. Smith, M. Lain, and M. Horowitz, "Boosting Beyond Static Scheduling in a Superscalar Processor," Proceedings of the 17th Annual International Symposium on Computer Architecture, June 1990. Google ScholarDigital Library
- MSmith92.M. Smith, M. Horowitz, and M. Lain, "Efficient Superscalar Performance Through Boosting," Fifth Interna. tional Conference on Architectural Support for Programming Languages and Operating Systems, September 1992. Google ScholarDigital Library
- Murakami89.K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction stream/Multiple instruction Pipelining): A novel High-Speed Single-Processor Architecture," Proceedings of the 16th Annual International Symposium on Computer Architecture, May 1989. Google ScholarDigital Library
- Nakajima91.Masaitsu Nakajima, et al."OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications'' Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991. Google ScholarDigital Library
- Nicolau85.A. Nicolau "Percolation Scheduling: A Parallel Compilation Technique" CS Technical Report TR 85-678, Cotnell University, Ithaca NY, May 1985. Google ScholarDigital Library
- Patt86.Y. Patt, et ai., "Run-Tune Generation of HPS Microinstructions From a VAX Instruction Stream," Micro 19 Workshop, New York, Oct. 1986. Google ScholarDigital Library
- Popescu91.V. Popescu, M. Schultz, J. Spracklen, G. Gibson, B. Lighmer, D. Isaman, 'The Metaflow Architecture," IEEE Micro, June 1991. Google ScholarDigital Library
- Singhal89.Ashok Singhal, "A High Performance Prolog Processor with Multiple Functional Units," Proceedings of the 16th Annual International Symposium on Computer Architecture, May 1989. Google ScholarDigital Library
- Slaven91.Gerrit A. Slavenburg, et al., "The LIFE Family of High Performance Single Chip VL1Ws," Hot Ch~s Ill Presentation, 1991.Google Scholar
- Thorton70.J.E. Thorton, "Design of a Computer-The Control Data 6600," Scott, Foresman and Co., Glenview IL 1970. Google ScholarDigital Library
- Tomasulo67.R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. Research Devel. opment, vol 11. pp.25-33, Jan. 1967.Google ScholarDigital Library
- Tyson92.G. Tyson, M. Fattens, and A. Pleszlom, "MISC: A Multiple Instruction Stream Computer," The 2$th Annual Inter. national Symposium on Microarchitecture, December 1992. Google ScholarDigital Library
- Wang91.Lingtao Wang and Chuan-lin Wu, "Distributed Instruction Set Computer Architecture," IEEE Trans. on Computers, voL 40, no. 8, Aug. 1991. Google ScholarDigital Library
- Wolfe91.Andrew Wolfe and John P. Shen, "A Variable Instruction Stream Extension to the VLFW Architecture,"The Fourth Conference on Architectural Support for Programming Languages and Operating Systems, April 1991. Google ScholarDigital Library
- Young85.Honesty Young, "Evaluation of a Decoupled Compurer Architecture and the Design of a Vector Extension," Computer Sciences Technical Report #603, University of Wisconsin- Madison, July 1985.Google Scholar
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