ABSTRACT
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach t o shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in High-level Descriptive Languages the (HDLs), Furthermore, the module generator can effectively generate a multiple-FPGA macro for large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Transfer-Level (RTL) description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.
- 1.M. Butts, J. Batcheller, and J. Varghese, "An Efficient Logic Emulation System," Proceedgng:~ o.f ICCD92, pp. 138-141, 1992. Google ScholarDigital Library
- 2.C. E. Cox and W. E. Blanz, "GANGLION- A Fast Field- Programmable (late Array Implementation of a Connectlonist Classifier," IEEE Journal on Solid-State C{rcu{ts, vol. 27, pp. 288-299, March 1992.Google Scholar
- 3.P. K. Chan, M. Schlag, and M. Martin, "BOR/3:A Reconfigurable Prototyping Board Using Field-Programmable Gate Arrays,'' in Proceedings of Is, International A CM/SIGDA Workshop on Field-Pro~ramrnable Gate Arrays, pp. 47-51, 1992.Google Scholar
- 4.S. Waiters, "Computer-Aided Prototyping for ASIC-Based Systerns," IEEE Design and Test of Computers, pp. 4-10, June 1991. Google ScholarDigital Library
- 5.D. E. Van den Bout, "The Anyboard: Programming and Enhancements,'' Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines 1993, pp. 68-77, 1993.Google Scholar
- 6.J. /jateley, "Logic Emulation Aids Design Process," A SIC EDA, July, 1994.Google Scholar
- 7.3. Kumar, N. Strader, J. Freeman, and M. Miller, "Emulation Verification of the Motorola 68080," Proceedings of ICCD, pp. 150-158, 1995. Google ScholarDigital Library
- 8.3./jateley et al., "UltraSPARC-i Emulation," Proceedings of the 32nd DAC, pp. 13-18, 1995. Google ScholarDigital Library
- 9.(3. /janapathy, R. Narayan,/3. Jorden, D. Fernandez, M. Wang, and J. Nishimura, "Hardware Emulation for Functional Verification of K5," Proceedings of the 33rd DAC, pp. 315-318, 1996. Google ScholarDigital Library
- 10.M. Butts, "Future Directions of Dynamically P. eprogrammable Systems," Proceedings of CICQ 1995.Google Scholar
- 11.XACT libraries guide, Xilinx, Inc., 1994.Google Scholar
- 12.D. Gajski, N. Dutt, A. Wu, and S. Lin, High-l~evel Synthesis, Kluwer Academic Publishers, 1992.Google ScholarCross Ref
- 13.R. Murgai, N. Shenoy, H. K. Bray,on, and A. Sangiovanni- Vincentelll, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proceedingz oJ ICCADgl, pp. 564-567, 1991.Google Scholar
- 14.C.M. Fiduccia and R. M. Mattheyses, A Linear Time Heuristic for Improving Network Partitions," Proceedings of 19th DAC, pp. 175-181, 1982. Google ScholarDigital Library
- 15.N.-C. Chou, L.-T. Liu, C.-K. Cheng, W.-J. Dai, and R. Lindelof, "Circuit Partitioning for Huge Logic Emulation Systems," Proceedings of the Slzt DAC, pp. 244-249, 1994. Google ScholarDigital Library
- 16.W.-J. Fang and A. C.-H. Wu, "A Hierarchical Functional Structuring and Partitioning Algorithm for Multiple-FPGA Implementations,'' ICCAD96, pp. 638-643, 1998. Google ScholarDigital Library
- 17.HDL- ICE User's Glzide, Version 1.0, January 1995, Quickturn Design Systems.Google Scholar
- 18.Quest Lrzerl~ Guide, Version 4.0, January 1995, Qulckturn Design Systems.Google Scholar
Index Terms
- Module generation of complex macros for logic-emulation applications
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