GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction

Abstract

Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near-individual LUT SRAM cell granularity, characterizing components with delays on the order of tens to a few hundred picoseconds with a resolution of ±3.2ps, matching the expected error bounds. This information reveals that the 65nm process used has, on average, random variation of σ μ =4.0% with components having an average maximum spread of 83ps. Timing Extraction also shows that as V_DD decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down, and variation increases from σ μ =4.3% to σ μ =5.8%, a clear indication that lowering V_DD magnifies the impact of random variation.

References

1. Altera. 2003. DE0-Nano Development and Education Board. http://www.altera.com/education/univ/materials/boards/de0-nano/unv-de0-nano-board.html.
2. Altera. 2005a. QUIP. http://www.altera.com/education/univ/research/quip/unv-quip.html. (2005).
3. Altera. 2005b. LCELL WYSIWYG Description for Cyclone II, Altera Corporation.
4. Altera. 2009. LCELL WYSIWYG Description for Cyclone III, Altera Corporation.
5. Arrow. 2009. BeMicro Embedded System Lab Instructions. http://www.arrownac.com/offers/altera-corporation/bemicro/BeMicro_Instructions_Embedded_System_Lab.pdf.
6. Chun Tak Chow, Lai Suen Mandy Tsui, Philip Heng Wai Leong, Wayne Luk, and Steven J. E. Wilton. 2005. Dynamic voltage scaling for commercial FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (December 2005), 173--180.
7. W. Bruce Culbertson, Rick Amerson, Richard Carter, Phil Kuekes, and Greg Snider. 1997. Defect tolerance on the TERAMAC custom computer. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. 116--123. DOI: http://dx.doi.org/10.1109/FPGA.1997.624611
8. Martin Eisele, Jorg Berthold, Doris Schmitt-Landsiedel, and Reinhard Mahnkopf. 1997. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, 4 (Dec. 1997), 360--368.
9. Benjamin Gojman, Nikil Mehta, Raphael Rubin, and André DeHon. 2011. Component-specific mapping for low-power operation in the presence of variation and aging. In Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Chapter 12, 381--432.
10. Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, and André DeHon. 2013. GROK-LAB: Generating real on-chip knowledge for intra-cluster delays using timing extraction. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 81--90.
11. Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, and Dinnis M. Sylvester. 2006. Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50, 4--5 (July/Sept. 2006), 469--490.
12. David Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Chris Lane, Andy Lee, and Philip Pan. 2009. Architectural enhancements in Stratix-III and Stratix-IV. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. ACM, 33--42.
13. Xiaochun Li, Jialing Tong, and Junfa Mao. 2010. Temperature-dependent device behavior in advanced CMOS technologies. In ISSSE, Vol. 2. 1--4. DOI: http://dx.doi.org/10.1109/ISSSE.2010.5606938
14. Mehrdad Majzoobi, Eva Dyer, Ahmed Elnably, and Farinaz Koushanfar. 2010. Rapid FPGA delay characterization using clock synthesis and sparse sampling. In Proceedings of International Test Conference. DOI: http://dx.doi.org/10.1109/TEST.2010.5699248
15. Larry McMurchie and Carl Ebeling. 1995. PathFinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 111--117.
16. Nikil Mehta, Raphael Rubin, and André DeHon. 2012. Limit study of energy & delay benefits of component-specific routing. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 97--106.
17. Jan M. Rabaey, Anantha P. Chandrakasan, and Borivoje Nikolic. 1999. Digital Integrated Circuits (2nd ed.). Prentice Hall.
18. Pete Sedcole, Justin S. Wong, and Peter Y. K. Cheung. 2008. Modelling and compensating for clock skew variability in FPGAs. In Proceedings of the International Conference on Field-Programmable Technology. 217--224. DOI: http://dx.doi.org/10.1109/FPT.2008.4762386
19. Jack R. Smith and Xia Tian. 2009. High-resolution delay testing of interconnect paths in Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement 58, 1 (2009), 187--195. DOI: http://dx.doi.org/10.1109/TIM.2008.927212
20. Ashish Srivastava, Dennis Sylvester, and David Blaauw. 2005. Statistical Analysis and Optimization for VLSI: Timing and Power. Springer.
21. Edward A. Stott, Justin S. J. Wong, Pete Pete Sedcole, and Peter Y. K. Cheung. 2010. Degradation in FPGAs: Measurement and modelling. In Proceedings of the International Symposium on Field-Programmable Gate Arrays. 229--238.
22. Terasic. 2011. ALTERA Cyclone IV Development & Education Board (DE0-Nano) http://wiki.ntb.ch/infoportal/_media/fpga/boards/de0_nano/de0-nano-schematic.pdf (2011).
23. Tim Tuan, Austin Lesea, Chris Kingsley, and Steven Trimberger. 2011. Analysis of within-die process variation in 65nm FPGAs. In Proceedings of the International Symposium on Quality Electronic Design. 1--5. DOI: http://dx.doi.org/10.1109/ISQED.2011.5770808
24. Justin S. Wong, Pete Sedcole, and Peter Y. K. Cheung. 2009. Self-measurement of combinatorial circuit delays in FPGAs. Transactions on Reconfigurable Technology and Systems 2, 2 (June 2009), 1--22. http://doi.acm.org/10.1145/1534916.1534920
25. Yun Ye, Samatha Gummalla, Chi-Chao Wang, Chaitali Chakrabarti, and Yu Cao. 2010. Random variability modeling and its impact on scaled CMOS circuits. Journal of Computational Electronics 9, 3--4 (Dec. 2010), 108--113. DOI: http://dx.doi.org/10.1007/s10825-010-0336-5
26. Haile Yu, Qiang Xu, and Philip H. W. Leong. 2010. Fine-grained characterization of process variation in FPGAs. In Proceedings of the International Conference on Field-Programmable Technology. 138--145. DOI: http://dx.doi.org/10.1109/FPT.2010.5681770

Index Terms

• Computer systems organization

  • Dependable and fault-tolerant systems and networks

• General and reference

  • Cross-computing tools and techniques

    • Performance

• Hardware

  • Electronic design automation

    • Physical design (EDA)

      • Placement

      • Wire routing

  • Hardware test

  • Robustness

• Networks

  • Network performance evaluation