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SEFOP: a novel approach to data path module placement

Published:07 November 1993Publication History
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References

  1. 1.M. lacoponi et al., "'A Hierarchical Gate Array Architecture and Design Methodology," IEEE Proc. 22rid DAC, 1985, pp439-442. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.C.K. Cheng and E.S. Kuh, "Module Placement Based on Resistive Network Optimization", IEEE Trans. on CAD, Vol. CAD3, No.3, 1984, pp218-225.Google ScholarGoogle Scholar
  3. 3.W.M. Dai and E.S. Kuh, "Simultaneous Floor Planning and Global Routing for Hierarchical Building Block Layout", IEEE Trans. on CAD, Vol. CAD6, No.5, 1987, pp828-837.Google ScholarGoogle Scholar
  4. 4.M. Marek-Sadowska, "Route Planner for Custom Chip Design", IEEE Proc. ICCAD, 1986, pp246-249.Google ScholarGoogle Scholar
  5. 5.S.G. Choi and C.M. Kyung, "A Floorplanning Algorithm Using Rectangular Voronol Diagram and Force-Directed Block Shaping", IEEE Proc. ICCAD, 1991, pp56-59.Google ScholarGoogle Scholar
  6. 6.Z Lengauer and R. Muller, "A Robot Framework for Hierarchical Floorplanning with Integrated Global Wiring", tEEE Proc. ICCAD, 1990, pp148-151.Google ScholarGoogle Scholar
  7. 7.J. Cong, "'Pin Assignment with Global Routing", 1EEE Proc. tCCAD, 1989, pp302-305.Google ScholarGoogle Scholar
  8. 8.D. Chen and C. Sechen, "'Mickey: a Macro Cell Global Router", Int. Workshop on Layout Synthesis, May 8-11,1990, MCNC, Research Triangle Park, NC. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.W. Swartz and C. Sechen, "'New Algorithms for Placement and Routing of Macro Cells", IEEE Proc. ICCAD, 1990, pp336-339.Google ScholarGoogle ScholarCross RefCross Ref
  10. 10.T.K. Ng, J. Oldfie.ld, and V. Pitchurnani, "Improvements of a Mincut Partition Algorithm", IEEE Proc. ICCAD, 1987, pp470-473.Google ScholarGoogle Scholar
  11. 11.C. Sechen and K.W. Lee, "'An Improved Simulated Annealing Algorithm for Row-Based Placement", IEEE Prec. ICCAD, 1987, pp478-481.Google ScholarGoogle Scholar
  12. 12.J.M. Kleinhans, G. Sigl, and F.M. Johannes, "'GORDIAN: A New Global Optimization Rectangle Dissection Method for Ceil Placement", IEEE Proc. ICCAD, 1988,pp506-509.Google ScholarGoogle ScholarCross RefCross Ref
  13. 13.G. Sigl, K. Doll, and EM. Johannes, "Analytical Placement: A Linear or a Quadratic Objective Function?", IEEE Proc. DA C, 1991, pp427-432. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. 14.W. K. Luk and A. A. Dean, "'Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout", IEEE Proc. DAC, 1989, pp110-115. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. 15.114. Hirsch and D. siewiorek, "'Automatically Extracting Structure from a Logical Design", IEEE Proc. 1CCAD, 1988, pp456-459.Google ScholarGoogle Scholar
  16. 16.G. Odawara, T. Hiraide, and O. Nishina, "Partitioning and Placement Technique for CMOS Gate Array", IEEE Trans. on CAD, Vol. CAD6, No.3, May 1987, pp335-363.Google ScholarGoogle Scholar

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  • Published in

    cover image ACM Conferences
    ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
    November 1993
    781 pages
    ISBN:0818644907

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    IEEE Computer Society Press

    Washington, DC, United States

    Publication History

    • Published: 7 November 1993

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