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Analysis of power consumption in memory hierarchies
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 239 - 242  
Year of Publication: 1997
ISBN:0-89791-903-3
Authors
Patrick Hicks  Pennsylvania State University
Matthew Walnock  Pennsylvania State University
Robert Michael Owens  Pennsylvania State University
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 26,   Citation Count: 16
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Meng-Fan Chang, Mary Jane Irwin, and Robert Michael Owens. Power-area trade-offs in memory arrays with dual word lines. Submitted to IEEE Symposium on Low Power Electronics 1997.
 
2
Patrick Hicks, Matthew Walnock, and Robert Michael Owens. Analysis of power consumption in memory hierarchies. Technical Report CSE-97-003, Pennsylvania State University Department of Computer Science and Engineering~ June 1997.
 
3
Mark Hill. Dinero IIi cache simulator, online document available via http://www.cs.wisc.edu/'markhill, 1989.
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T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago. Evaluation of architecture-level power estimation for CMOS RISC processors. In IEEE Syrup on Low Power Electronics, pages 44-45, 1995.
 
7
Y. Shimazaki et al. An automatic-power-save cache memory for low-power RISC processors. In IEEE ~ym. posium on Low Power Electronics, pages 58-59, 1995.
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CITED BY  16
 
 
 
 
Collaborative Colleagues:
Patrick Hicks: colleagues
Matthew Walnock: colleagues
Robert Michael Owens: colleagues

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