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FPGA Implementations for Volterra DFEs

Published: 02 October 2014 Publication History

Abstract

In this paper a high-throughput FPGA implementation of a Volterra-based Decision Feedback Equalizer (DFE) is presented for first time. The DFE is a popular scheme, and its performance is a critical issue in high-speed communication systems. To overcome the throughput limitation due to the feedback loop, two multiplexer-based architectures were developed and compared. The introduced architectures were implemented on two Xilinx FPGAs, exploiting the specific features of these devices. Based on the experimental results, it is proved that the introduced designs achieve high throughput (10Gb/s), showing that the FPGAs are a suitable option for high-speed systems (e.g. optical communication systems).

References

[1]
M. Li, S. Wang, J. Chen, and T. Kwasniewski, "Design and optimization of multi-tap DFE for high-speed backplane data communications," in Proc. IEEE PACRIM Comm., Comp. and signal Processing, pp. 601--604, Aug. 2005.
[2]
C. A. Belfiore and J. John H. Park, "Decision feedback equalizer," IEEE Trans. Commun. Technol., vol. 67, no. 8, pp. 1143--1156, 1979.
[3]
G. O. Glentis, K. Georgoulakis, C. Matrakidis, "Performance evaluation of Decision Feedback Equalizers in fiber communication links" in Int. Symp. On Communications, Control and Signal Processing, 2014.
[4]
C. Xia and W. Rosenkranz, "Nonlinear electrical equalization for different modulation formats with optical filtering," J. Lightwave Tech., vol. 25, no. 4, pp. 996--1001, 2007.
[5]
J. Pan and C. Cheng, "Wiener-hammerstein model based electrical equalizer for optical communications systems," J. Lightwave Tech., vol. 29, pp. 2454--2459, 2011.
[6]
M. Renfors and Y. Neuvo, "The maximum sampling rate of digital filters under hardware speed constraints," IEEE Trans. Circuits Syst. II, vol. 28, pp. 196--202, 1981.
[7]
K. K. Parhi, "Design of multigigabit multiplexer-loop-based decision feedback equalizers," IEEE Trans. VLSI Syst., vol. 13, no. 4, pp. 489--493, 2005.
[8]
C.-H. Lin, A.-Y. Wu, and F.-M. Li, "High-performance VLSI architecture of decision feedback equalizer for gigabit systems," IEEE Trans. Circuits Syst. II, vol. 53, pp. 911--915, 2006.
[9]
Yu-Chun Lin; Muh-Tian Shiue; Shyh-Jye Jou, "10Gbps decision feedback equalizer with dynamic lookahead decision loop," in Int Symp. on Circuits and Systems (ISCAS), pp.1839,1842, 2009.
[10]
D. Oh and K. K. Parhi, "Low complexity design of high speed parallel decision feedback equalizers," IEEE Conf. on Application-Specific Systems, Architectures and Processors (ASAP), pp. 118--124, Sep. 2006.
[11]
G. O. Glentis, Y. Kopsinis, K. Georgoulakis, C. Matrakidis, "Electronic dispersion compensation of fiber links using sparsity induced Volterra equalizers" in Int. Symp. on Signal Processing and Information Technology (ISSPIT), 2013.
[12]
Xilinx Inc., "7 Series DSP48E1 Slice", User Guide, Available: http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf. Accessed: May 2014

Cited By

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  • (2021)High-performance low-complexity Volterra decision feedback equalizer based on FPGA for C-Band PAM-4 transmissionOptical Fiber Technology10.1016/j.yofte.2021.10255564(102555)Online publication date: Jul-2021

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Published In

cover image ACM Other conferences
PCI '14: Proceedings of the 18th Panhellenic Conference on Informatics
October 2014
355 pages
ISBN:9781450328975
DOI:10.1145/2645791
  • General Chairs:
  • Katsikas Sokratis,
  • Hatzopoulos Michael,
  • Apostolopoulos Theodoros,
  • Anagnostopoulos Dimosthenis,
  • Program Chairs:
  • Carayiannis Elias,
  • Varvarigou Theodora,
  • Nikolaidou Mara
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

  • Greek Com Soc: Greek Computer Society
  • Univ. of Piraeus: University of Piraeus
  • National and Kapodistrian University of Athens: National and Kapodistrian University of Athens
  • Athens U of Econ & Business: Athens University of Economics and Business

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 October 2014

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Author Tags

  1. Decision Feedback Equalizer
  2. FPGA
  3. Volterra filter

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  • Refereed limited

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PCI '14

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PCI '14 Paper Acceptance Rate 51 of 102 submissions, 50%;
Overall Acceptance Rate 190 of 390 submissions, 49%

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Cited By

View all
  • (2021)High-performance low-complexity Volterra decision feedback equalizer based on FPGA for C-Band PAM-4 transmissionOptical Fiber Technology10.1016/j.yofte.2021.10255564(102555)Online publication date: Jul-2021

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