Validating SystemC Implementations Against Their Formal Specifications

ABSTRACT

The ever increasing complexity of embedded systems leads to a constant strive for higher levels of abstraction. While the design at the Electronic System Level (ESL) with SystemC as the common programming language is state-of-the-art today, also the use of formal specifications by means of modeling languages such as UML or SysML receives more and more attention. This raises the question of how to validate an ESL implementation against a given formal specification. For this, SystemC's limited introspection and reflection features pose a serious obstacle. In this paper, a methodology is presented that retrieves the necessary static and dynamic information which is needed in order to validate a SystemC design. For this purpose, we retrieve information from the SystemC API and compiler-generated debug symbols. The proposed solution can be applied to a wide variety of project setups and requires only minimal adjustments to retrieve the necessary information.

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Index Terms

• Hardware

  • Electronic design automation

    • Physical design (EDA)

  • Emerging technologies

  • Hardware validation

  • Very large scale integration design