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Slow Down or Halt: Saving the Optimal Energy for Scalable HPC Systems

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Published:31 January 2015Publication History

ABSTRACT

The presence of pervasive slack provides ample opportunities for achieving energy efficiency for HPC systems nowadays. Regardless of communication slack, classic energy saving approaches for saving energy during the slack otherwise include race-to-halt and CP-aware slack reclamation, which reply on power scaling techniques to adjust processor power states judiciously during the slack. Existing efforts demonstrate CP-aware slack reclamation is superior to race-to-halt in energy saving capability. In this paper, we formally model our observation that the energy saving capability gap between the two approaches is significantly narrowed down on today's processors, given that state-of-the-art CMOS technologies allow insignificant variation of supply voltage as operating frequency of a processor scales. Experimental results on a large-scale power-aware cluster validate our findings.

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  • Published in

    cover image ACM Conferences
    ICPE '15: Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering
    January 2015
    366 pages
    ISBN:9781450332484
    DOI:10.1145/2668930

    Copyright © 2015 ACM

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    New York, NY, United States

    Publication History

    • Published: 31 January 2015

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    ICPE '15 Paper Acceptance Rate23of74submissions,31%Overall Acceptance Rate252of851submissions,30%

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