Timing driven placement in interaction with netlist transformations

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Timing driven placement in interaction with netlist transformations

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 36 - 41

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Guenter Stenz	Institute of Electronic Design Automation, Technical University of Munich, 80333 Munich, Germany
Bernhard M. Riess	Siemens AG, Semiconductor Group, 81617 Munich, Germany
Bernhard Rohfleisch	Siemens AG, Semiconductor Group, 81617 Munich, Germany
Frank M. Johannes	Institute of Electronic Design Automation, Technical University of Munich, 80333 Munich, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 19, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Massoud Pedram , Narasimha Bhat, Layout driven technology mapping, Proceedings of the 28th conference on ACM/IEEE design automation, p.99-105, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127635]
	3	M. Pedram and N. Bhat, "Layout driven logic restructuring/decomposition," in IEEE/A CM International Conference on Computer-Aided Design (IC. CAD), pp. 134-137, 1991.
	4	Hirendu Vaishnav , Massoud Pedram, Routability-driven fanout optimization, Proceedings of the 30th international conference on Design automation, p.230-235, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164684]
	5	Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196399]
	6	Weitong Chuang , Ibrahim N. Hajj, Delay and area optimization for compact placement by gate resizing and relocation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.145-148, November 06-10, 1994, San Jose, California, United States
	7	S. Liu, K. Pan, M. Pedram, and A. M. Despain, "A1- leviating routing congestion by combining logic resynthesis and linear placement," in European Conference on Design Automation (EDA C), pp. 578--582, 1993.
	8	Wei-Liang Lin , M. Sarrafzadeh , C. K. Wong, The reproducing placement problem with applications, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.686-689, November 06-10, 1994, San Jose, California, United States
	9	B.M. Riess and G. G. Ettelt, "Speed: Fast and efficient timing driven placement," in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 377-380, 1995.
	10	J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal delay in rc tree networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, pp. 202-211, 1983.
	11	K. Doll, :F. M. Johannes, and K. J. Antreich, "Iterative placement improvement by network flow methods," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1190-- 1200~ Oct. 1994.

CITED BY 14

	Deshanand P. Singh , Stephen D. Brown, An area-efficient timing closure technique for FPGAs using Shannon's expansion, Integration, the VLSI Journal, v.40 n.2, p.167-173, February, 2007
	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, A timing-driven soft-macro resynthesis method in interaction with chip floorplanning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.262-267, June 21-25, 1999, New Orleans, Louisiana, United States
	Hema Kapadia , Mark Horowitz, Using partitioning to help convergence in the standard-cell design automation methodology, Proceedings of the 36th ACM/IEEE conference on Design automation, p.592-597, June 21-25, 1999, New Orleans, Louisiana, United States
	Thomas Kutzschebauch , Leon Stok, Congestion aware layout driven logic synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Wilsin Gosti , Amit Narayan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Wireplanning in logic synthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.26-33, November 08-12, 1998, San Jose, California, United States
	Min Pan , Chris Chu, FastRoute: a step to integrate global routing into placement, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Chen Li , Cheng-Kok Koh , Patrick H. Madden, Floorplan management: incremental placement for gate sizing and buffer insertion, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	A. Ranjan , A. Srivastava , V. Karnam , M. Sarrafzadeh, Layout aware retiming, Proceedings of the 11th Great Lakes symposium on VLSI, p.25-30, March 2001, West Lafayette, Indiana, United States
	Wilsin Gosti , Sunil P. Khatri , Alberto L. Sangiovanni-Vincentelli, Addressing the timing closure problem by integrating logic optimization and placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Ron Ho , Ken Mai , Hema Kapadia , Mark Horowitz, Interconnect scaling implications for CAD, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.425-429, November 07-11, 1999, San Jose, California, United States
	Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
	Stephen M. Plaza , Igor L. Markov , Valeria Bertacco, Optimizing non-monotonic interconnect using functional simulation and logic restructuring, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001