Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis

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Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 48 - 53

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Glenn Holt	Department of Computer Science, Iowa State University
Akhilesh Tyagi	Department of Computer Science, Iowa State University

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 24, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BM82	R. Brayton and C. McMullen. The decomposition and factorization of boolean expressions. In Proceedings of the International Symposium on Circuits and Systems, pages 49-54, 1982.
	CKL94	jason Cong, Cheng-Kok Koh, and Kwok-Shing Leung. Wiresizing with driver sizing for performance and power optimization. In International Symposium on Low Power Design, 1994.
	CPM+95	Anantha P. Chandrakasan, Miodrang Potkonjak, Renu Mehra, Jan Rabaey, and Robert W. Broderson. Optimizing power using transformations. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 14(1):12-30, 1995.
	CSB92	Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Broderson. Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, 27, April 1992.
	GDKW92	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	HT95	G. Holt , A. Tyagi, EPNR: an energy-efficient automated layout synthesis package, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.224-229, October 02-04, 1995
	IP95	Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217537]
	Keu87	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	Len90	Thomas Lengauer, Combinatorial algorithms for integrated circuit layout, John Wiley & Sons, Inc., New York, NY, 1990
	Naj91	Farid N. Najm, Transition density, a stochastic measure of activity in digital circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.644-649, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127744]
	Ous85	John Ousterhout. MAGIC Tutorial. Department of Electrical Engineering and Computer Science, University of California, Berkeley. 1985.
	PB91a	Massoud Pedram and Narasimha Bhat. Layout driven logic restructuring}decomposition. In Proceedings of the IEEE Conference on Computer Aided Design, pages 134-137. IEEE, 1991.
	PB91b	Massoud Pedram , Narasimha Bhat, Layout driven technology mapping, Proceedings of the 28th conference on ACM/IEEE design automation, p.99-105, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127635]
	RS93	Kaushik Roy and Prasad S.C. Circuit activity based logic synthesis for low power reliable operations. IEEE Transactions on VLSI Systems, 1(4):503-513, 1993.
	Rud89	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	S+92	E.M. Seatovicb et al. SIS: A system for sequential circuit synthesis. Memorandum UCB/ERL M92/41, Department of Electrical Engineering and Computer Science, University of California, Berkeley, May 1992.
	Tho79	C. D. Thompson, Area-time complexity for VLSI, Proceedings of the eleventh annual ACM symposium on Theory of computing, p.81-88, April 30-May 02, 1979, Atlanta, Georgia, United States [doi>10.1145/800135.804401]
	VP93	H. Vaishnav and M. Pedram. PCUBE: a performance driven placement algorithm for low power designs. In Proceedings of the European Design Automation Conference, pages 72-77. ACMIEEE, 1993.
	VTR95	V. Veeramachneni. A. Tyagi, and S. Rajagopal. State assignment reencoding for low-power FSMs. In International Symposium on Low Power Design. 1995.

CITED BY 2

	Kevin Oo Tinmaung , David Howland , Russell Tessier, Power-aware FPGA logic synthesis using binary decision diagrams, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, A timing-driven soft-macro resynthesis method in interaction with chip floorplanning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.262-267, June 21-25, 1999, New Orleans, Louisiana, United States