Bo Wang
ABSTRACT
The paper presents a VLSI architecture of a reconfigurable processor. The proposed architecture can efficiently implement symmetric ciphers, while maintaining flexibility through reconfiguration. A series of optimization methods are introduced during this process. The InterConnection Tree between Rows (ICTR) decreases the area overhead through reducing the complexity of interconnection. The use of the Hierarchical Context Organization (HCO) scheme reduces the total size of contexts and increases the speed of dynamic configuration. The proposed architecture has the ability of implementing most symmetric ciphers, such as AES, DES, SHACAL-1, SMS4 and ZUC, etc. The performance, area efficiency (throughput/area) and energy efficiency (throughput/power) of the proposed architecture have obvious advantages over the state-of-the-art architectures in literatures.
Index Terms
- REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only)
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