Effective communication for a system of cluster-on-a-chip processors
Pages 122 - 131
Abstract
In this work, we analyze efficient communication methods for a grid of many-core processors in the absence of cache coherence. For this study, we build a multi-chip processor with 240 tightly connected cores and demonstrate its scalability. This processor is based on the Intel SCC, a cluster-on-a-chip research processor with 48 non-coherent memory coupled cores. Our new research system virtually extends the on-chip network of multiple SCC systems and provides new communication functionality for direct on-chip memory access. We analyze access patterns of different communication schemes and apply techniques to hide latency, such as offloading communication and software caching with relaxed consistency.
References
[1]
D. Bailey, E. Barszcz, J. Barton, D. Browning, R. Carter, R. Fatoohi, P. Frederickson, T. Lasinski, R. Schreiber, H. Simon, V. Venkatakrishnan, and S. Weeratunga. The NAS parallel benchmarks. Intl. journal of supercomputer applications, 5(3):66--73, 1991.
[2]
S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook. TILE64 - processor: a 64-core SoC with mesh interconnect. In Solid-state circuits conference, 2008. ISSCC 2008. digest of technical papers. IEEE international, Feb. 2008, pp. 588--598.
[3]
C. Clauss, S. Lankes, P. Reble, and T. Bemmerl. Evaluation and improvements of programming models for the Intel SCC many-core processor. In Proceedings of the 2011 international conference on high performance computing and simulation. In HPCS. Istanbul, Turkey, July 2011, pp. 525--532.
[4]
C. Clauss, S. Lankes, P. Reble, J. Galowicz, S. Pickartz, and T. Bemmerl. iRCCE: a non-blocking communication extension to the RCCE communication library for the intel single-chip cloud computer. Users Guide and API Manual (Version 2.0). Chair for Operating Systems, RWTH Aachen University, Mar. 2013.
[5]
B. K. Daya, C.-H. O. Chen, S. Subramanian, W.-C. Kwon, S. Park, T. Krishna, J. Holt, A. P. Chandrakasan, and L.-S. Peh. SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In Proceedings of the 41st international symposium on computer architecture, ISCA 2014. Minneapolis, MN, USA, July 2014.
[6]
M. Gries, U. Hoffmann, M. Konow, and M. Riepen. SCC: a flexible architecture for many-core platform research. Computing in science & engineering, 13(6):79--83, 2011.
[7]
R. W. Hockney. The communication challenge for MPP: Intel Paragon and Meiko CS-2. Parallel computing, 20(3):389--398, Mar. 1994. ISSN: 0167-8191.
[8]
B. Joó, D. Kalamkar, K. Vaidyanathan, M. Smelyanskiy, K. Pamnany, V. Lee, P. Dubey, and I. Watson W. Lattice QCD on Intel Xeon Phi Coprocessors. In, Supercomputing. Vol. 7905, in Lecture Notes in Computer Science, pp. 40--54. Springer Berlin Heidelberg, 2013. ISBN: 978-3-642-38749-4.
[9]
T. Mattson and R. van der Wijngaart. RCCE: a small library for many-core communication. Version 2.0. Intel Corporation, Jan. 2011. URL: http://communities.intel.com/docs/DOC-5628.
[10]
T. Mattson, R. van der Wijngaart, M. Riepen, T. Lehnig, P. Brett, W. Haas, P. Kennedy, J. Howard, S. Vangal, N. Borkar, G. Ruhl, and S. Dighe. The 48-core SCC processor: the programmer's view. In Proceedings of the 2010 ACM/IEEE conference on supercomputing (SC10). New Orleans, LA, USA, Nov. 2010.
[11]
S. Pakin, M. Lang, and D. K. Kerbyson. The reverse-acceleration model for programming petascale hybrid systems. IBM journal of research and development, 53(5):721--735, Sept. 2009. ISSN: 0018-8646.
[12]
S. Potluri, A. Venkatesh, D. Bureddy, K. Kandalla, and D. Panda. Efficient intra-node communication on Intel-MIC clusters. In Proceedings of 13th IEEE/ACM international symposium on cluster, cloud and grid computing (CCGrid), May 2013, pp. 128--135.
[13]
P. Reble, C. Clauss, M. Riepen, S. Lankes, and T. Bemmerl. Connecting the cloud: transparent and flexible communication for a cluster of Intel SCCs. In Proceedings of the many-core applications research community (MARC) symposium at the RWTH Aachen University. Germany, Dec. 2012, pp. 13--19. ISBN: 978-300-039545-1.
[14]
P. Reble and G. Wassen. Towards predictability of operating system supported communication for PCIe based clusters. In, Euro-par 2013: parallel processing workshops. Vol. 8374, in Lecture Notes in Computer Science, pp. 833--842. Springer Berlin Heidelberg, 2014. ISBN: 978-3-642-54419-4.
[15]
SCC external architecture specification (EAS). Revision 1.1. Intel Corporation, Nov. 2010. URL: http://communities.intel.com/docs/DOC-5852.
[16]
M. van Tol, R. Bakker, M. Verstraaten, C. Grelck, and C. Jesshope. Efficient memory copy operations on the 48-core Intel SCC processor. In Proceedings of the 3rd marc symposium. KIT Scientific Publishing, Ettlingen, Germany, July 2011, pp. 13--18. ISBN: 978-3-86644-717-2.
- Effective communication for a system of cluster-on-a-chip processors
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Published: 07 February 2015
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PPoPP '15: 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
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Overall Acceptance Rate 53 of 97 submissions, 55%
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