skip to main content
10.1145/2744769.2744802acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Avoiding transitional effects in dynamic circuit specialisation on FPGAs

Published:07 June 2015Publication History

ABSTRACT

Dynamic Circuit Specialisation (DCS) is a technique that uses the reconfigurability of an FPGA to optimise a circuit during run-time, thus achieving higher performance and lower resource cost. However, run-time reconfiguration causes transitional effects that form an important problem for DCS. Because of these, the DCS circuit cannot be used while it is being reconfigured. This limits the usability of DCS for streaming applications and other applications that cannot tolerate downtime. For other applications, this results in a loss of performance.

In this paper, we present a technique to perform partial reconfiguration for DCS without transitional effects, thus allowing the circuit to remain fully functional at all times. The proposed method performs DCS by reconfiguring only LookUp Tables of the FPGA and does not require changes to the configuration architecture of the FPGA. The approach was tested and evaluated on current Xilinx FPGAs.

References

  1. F. Abouelella, T. Davidson, W. Meeus, K. Bruneel, and D. Stroobandt. How to Efficiently Implement Dynamic Circuit Specialization Systems. ACM Transactions on Design Automation of Electronic Systems, 18(3):35:1--35:38, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. M. Bolotski, A. DeHon, and T. Knight Jr. Unifying FPGAs and SIMD arrays. In 2nd International Workshop on Field-Programmable Gate Arrays, 1994.Google ScholarGoogle Scholar
  3. K. Bruneel, W. Heirman, and D. Stroobandt. Dynamic Data Folding with Parameterizable FPGA Configurations. ACM Transactions on Design Automation of Electronic Systems (TODAES), 16(4):43:1--43:29, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. K. Bruneel and D. Stroobandt. TROUTE: a reconfigurability-aware FPGA router. Lecture Notes in Computer Science, 5992:207--218, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. T. Davidson, F. Abouelella, K. Bruneel, and D. Stroobandt. Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment. International Journal of Reconfigurable Computing, pages 5:5--5:5, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. A. DeHon, T. Knight Jr., E. Tau, M. Bolotski, I. Eslick, D. Chen, and J. Brown. Patent: Dynamically Programmable Gate Array With Multiple Contexts, 1998.Google ScholarGoogle Scholar
  7. Ghent University, HES Group. TLUT tool flow. https://github.com/UGent-HES/tlut_flow.Google ScholarGoogle Scholar
  8. S. Hauck. Configuration prefetch for single context reconfigurable coprocessors. In Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, pages 65--74, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. A. Kulkarni, K. Heyse, T. Davidson, and D. Stroobandt. Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs. In FPGAworld Conference, 2014.Google ScholarGoogle Scholar
  10. A. Lam, S. J. E. Wilton, P. Leong, and W. Luk. An analytical model describing the relationships between logic architecture and FPGA Density. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, pages 221--226, 2008.Google ScholarGoogle ScholarCross RefCross Ref
  11. R. T. Ong and Xilinx. Patent: Programmable Logic Device Which Stores More Than One Configuration And Means For Switching Configurations, 1995.Google ScholarGoogle Scholar
  12. M. J. Wirthlin and B. Hutchings. Improving functional density through run-time constant propagation. In Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, pages 86--92, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Xilinx. LogiCORE IP XPS HWICAP (v5.01.a), 2011.Google ScholarGoogle Scholar

Index Terms

  1. Avoiding transitional effects in dynamic circuit specialisation on FPGAs

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in
        • Published in

          cover image ACM Conferences
          DAC '15: Proceedings of the 52nd Annual Design Automation Conference
          June 2015
          1204 pages
          ISBN:9781450335201
          DOI:10.1145/2744769

          Copyright © 2015 ACM

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 7 June 2015

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • research-article

          Acceptance Rates

          Overall Acceptance Rate1,770of5,499submissions,32%

          Upcoming Conference

          DAC '24
          61st ACM/IEEE Design Automation Conference
          June 23 - 27, 2024
          San Francisco , CA , USA
        • Article Metrics

          • Downloads (Last 12 months)0
          • Downloads (Last 6 weeks)0

          Other Metrics

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader