ABSTRACT
DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features a 500 MHz clock speed and a high-bandwidth system interface that channels up to 5.3 Gbytes/second of cache data and 2.6 Gbytes/second of main-memory data into the processor. Simulation-based functional verification was performed on the logic design using implementation-directed, pseudo-random exercisers, supplemented with implementation-specific, hand-generated tests. Extensive functional coverage analysis was performed to grade and direct the verification effort. The success of the verification effort was underscored by first prototype chips which were used to boot multiple operating systems across several different prototype systems.
- 1.Linley Gwennap, "Digital 21264 Sets New Standard," Microprocessor Report (October 28, 1996): 11-16.Google Scholar
- 2.Mike Kantrowitz and Lisa Noack, "Functional Verification of a Multiple-issue, Pipelined, Superscalar Alpha Processor ~ -- the Alpha 21164 CPU Chip," Digital Technical Journal, vol. 7, no. 1 (1995): 136-143. Google ScholarDigital Library
- 3.W. Anderson, "Logical Verification of the NVAX CPU Chip Design," Digital Technical Journal, vol. 4, no. 3 (Summer 1992): 38-46.Google Scholar
- 4.A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-random Test Program Generator,"lBM Systems Journal, vol. 30, no. 4 (1991): 527-538. Google ScholarDigital Library
- 5.A. Ahi, G. Burroughs, A. Gore, SLaMar, C-Y. Lin, and A. Wiemann, "Design Verification of the HP 9000 Series 700 PA-RISC Workstations," ttewlett-Packard Journal (August 1992): 34-42.Google Scholar
- 6.D. Wood, G. Gibson, and R. Katz, "Verifying a Multiprocessor Cache Controller Using Random Test Generation," IEEE Design and Test of Computers(August 1990): 13-25. Google ScholarDigital Library
Index Terms
- Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor
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