research-article

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM

Authors:
Youngsik Kim

Pohang University of Science and Technology, Korea

Pohang University of Science and Technology, Korea
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,
Sungjoo Yoo

Seoul National University, Korea

Seoul National University, Korea
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,
Sunggu Lee

Pohang University of Science and Technology, Korea

Pohang University of Science and Technology, Korea
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ACM Transactions on Design Automation of Electronic Systems Volume 21 Issue 2Article No.: 23pp 1–27https://doi.org/10.1145/2820610

Published:28 January 2016Publication History

ACM Transactions on Design Automation of Electronic Systems

Abstract

Multi-level cell (MLC) phase change RAM (PRAM) is expected to offer lower cost main memory than DRAM. However, poor write performance is one of the most critical problems for practical applications of MLC PRAM. In this article, we present two schemes to improve write performance by controlling the target resistance distribution of MLC PRAM cells. First, we propose multiple RESET/SET operations that relax the target resistance bands of intermediate logic levels with additional RESET/SET operations, which reduces the program time of intermediate logic levels, thereby improving write performance. Second, we propose a two-step write scheme consisting of lightweight write and idle-time completion write that exploits the fact that hot dirty data tend to be overwritten in a short time period and the MLC PRAM often has long idle times. Experimental results show that the multiple RESET/SET and two-step write schemes result in an average IPC improvement of 15.7% and 10.4%, respectively, on a hybrid DRAM/PRAM main memory subsystem. Furthermore, their integrated solution results in an average IPC improvement of 23.2% (up to 46.4%).

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Index Terms

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Reviews

Reviewer: Dounia Khaldi

Memory technology is important to everyone who wants his computer to be faster. Dynamic random-access memory (DRAM) has been used as the main memory technology for decades, but it has some overhead related to its cost and power consumption. Research in this domain continues to find alternative solutions that provide the same or better performance, but with lower cost and lower power consumption. Phase-change RAM (PRAM) technology is one of these alternatives, but has poor write performance. This paper proposes two techniques to improve the write performance of the hybrid PRAM/DRAM system. First, multiple RESET/SET operations are proposed to reduce the latency for intermediate logic levels. Also, a two-step write scheme is adopted to perform a first lightweight write that has short retention time; then, during idle time, the lifetime of this data under lightweight write is increased by performing a completion write. This paper will be interesting to computer scientists who are developing high-scale scientific applications in different domains such as biology, physics, chemistry, medicine, and so on, and need to know about the current research and future directions with regard to memory technology. This will make it possible to tune algorithms to make the best use of memory. Online Computing Reviews Service

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Published in
ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 2
January 2016
422 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/2888405
Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea
Issue’s Table of Contents
Copyright © 2016 ACM
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Publication History
- Published: 28 January 2016
- Accepted: 1 September 2015
- Revised: 1 July 2015
- Received: 1 March 2015
Published in todaes Volume 21, Issue 2

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Phase change RAM
multi-level cell
resistance distribution
write performance
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Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM

ACM Transactions on Design Automation of Electronic Systems

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Cited By

Index Terms

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Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System

Compiler directed write-mode selection for high performance low power volatile PCM

Reviews

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