Modeling performance and energy for applications offloaded to Intel Xeon Phi

ABSTRACT

Accelerators are adopted to increase performance, reduce time-to-solution, and minimize energy-to-solution. However, employing them efficiently, given system and application characteristics, is often a daunting task. A goal of this work is to propose a general model that predicts performance and power requirements for an application, computational portions of which are offloaded to an accelerator. Intel Xeon Phi is the only accelerator type investigated here, and only in offload execution mode. This mode is also employed by other accelerator types, such as GPU; thus the proposed model is applicable directly. The predictive capabilities of the model are demonstrated by determining the best hardware-software configuration instances with respect to the minimum energy consumption for the CoMD proxy application executed on single or multiple nodes. For the CoMD problem sizes investigated here, the best modeled configuration was relatively close to the best measured configuration with relative error under 5% of the energy consumed for most configurations. Initial model validation also confirmed the model accuracy for a variety of model parameters, such as host computation time and power consumption on the host and accelerator. The model also provides estimates of the total data movement and computational throughput as well as of some key metrics, such as FLOPs-per-joule and bytes-per-joule, which are commonly used to study the energy-performance trade-offs.

References

1. S. Cepeda. Optimization and performance tuning for Intel Xeon Phi coprocessors, part 2: Understanding and using hardware events, 2012. https://software.intel.com/en-us/articles/.
2. J. Choi, M. Mukhan, X. Liu, and R. Vudue. Algorithmic time, energy, and power on candidate HPC compute building blocks. In 2014 IEEE 28th International Symposium on Parallel Distributed Processing (IPDPS), Arizona, USA, May 2014.
3. J. W. Choi, D. Bedard, R. Fowler, and R. Vuduc. A roofline model of energy. In Parallel Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 661--672, May 2013.
4. K. Choi, R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Jan 2005.
5. M. Corden. How to compile for Intel AVX, 2012. https://software.intel.com/en-us/articles/how-to-compile-for-intel-avx.
6. DOE. Co-design, 2013. http://science.energy.gov/ascr/research/scidac/co-design/.
7. ExMatEx. CoMD proxy application, 2012. http://www.exmatex.org/comd.html.
8. R. Hayashi and S. Horiguchi. Domain decomposition scheme for parallel molecular dynamics simulation. In High Performance Computing on the Information Superhighway, 1997. HPC Asia '97, pages 595--600, Apr 1997.
9. ICL:UT. Performance application programming interface PAPI, 2015. http://icl.cs.utk.edu/papi/.
10. Intel. How to use huge pages to improve application performance on pIntel Xeon Phi coprocessor, 2012. https://software.intel.com/sites/default/files/Large_pages_mic_0.pdf.
11. G. Lawson, M. Sosonkina, and Yuzhong S. Energy evaluation for applications with different thread affinities on the Intel Xeon Phi. In Computer Architecture and High Performance Computing Workshop (SBAC-PADW), 2014 International Symposium on, Oct 2014.
12. G. Lawson, M. Sosonkina, and Y. Shen. Performance and energy evaluation of CoMD on Intel Xeon Phi co-processors. In Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, Co-HPC '14, Piscataway, NJ, USA, 2014. IEEE Press. http://dx.doi.org/10.1109/Co-HPC.2014.12.
13. G. Lawson, M. Sosonkina, and Y. Shen. Changing CPU frequency in CoMD proxy application offloaded to Intel Xeon Phi co-processors. Procedia Computer Science, 51(0):100--109, 2015. International Conference On Computational Science, ICCS 2015.
14. G. Lawson, M. Sosonkina, and Y. Shen. Towards modeling energy consumption of Xeon Phi. CoRR, abs/1505.06539, 2015. http://arxiv.org/abs/1505.06539.
15. G. Lawson, V. Sundriyal, M. Sosonkina, and Y. Shen. Experimentation procedure for offloaded mini-apps executed on cluster architectures with Xeon Phi accelerators, 2015. http://arxiv.org/abs/1509.02135.
16. B. Li, H. Chang, S. L. Song, C. Su, T. Meyer, J. Mooring, and K. Cameron. The power-performance tradeoffs of the Intel Xeon Phi on HPC applications, 2014. http://scape.cs.vt.edu/wp-content/uploads/2014/06/lspp14-Li.pdf.
17. J. Mohd-Yusof, S. Swaminarayan, and T. C. Germann. Co-design for molecular dynamics: An exascale proxy application, 2013. http://www.lanl.gov/orgs/adtsc/publications/science_highlights_2013/docs/Pg88_89.pdf.
18. Y. S. Shao and D. Brooks. Energy characterization and instruction-level energy model of Intel's Xeon Phi processor, 2013. http://www.eecs.harvard.edu/~shao/papers/shao2013-islped.pdf.
19. V. Sundriyal and M. Sosonkina. Analytical modeling of the CPU frequency to minimize energy consumption in parallel applications. Submitted for publication to: Elsevier, 2015.
20. S. Williams, A. Waterman, and D. Patterson. Roofline: An insightful visual performance model for multicore architectures. Commun. ACM, 52(4):65--76, April 2009. http://doi.acm.org/10.1145/1498765.1498785.

Index Terms

• Computer systems organization

  • Dependable and fault-tolerant systems and networks

• General and reference

  • Cross-computing tools and techniques

    • Performance

• Hardware

  • Hardware validation

• Networks

  • Network performance evaluation