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Rethinking Memory System Design (along with Interconnects)

Published: 05 December 2015 Publication History

Abstract

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck [27, 28]. At the same time, DRAM technology is experiencing difficult circuit and device scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques (see, for example [7, 8, 11, 12, 15, 17, 18, 22, 23, 32]).
In this talk, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of the memory and the rest of the system, including interconnects (e.g., [1, 2, 19, 20, 34-36]), 2) designing a memory system that intelligently employs multiple memory technologies and coordinates memory and storage management using non-volatile memory technologies (e.g., [16-18, 24, 25, 32, 33, 40-42]), 3) providing predictable performance and QoS to applications sharing the memory system (e.g., [3, 9, 10, 13, 14, 26, 29, 37-39]). As we discuss challenges and solution directions in memory, we will point out research opportunities in interconnects and memory-interconnect co-design (e.g., [2, 4-6, 19, 21, 30, 31]).

References

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L. Subramanian et al. The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory. In MICRO, 2015.
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J. Zhao et al. FIRM: Fair and high-performance memory control for persistent memory systems. In MICRO, 2014.

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  1. Rethinking Memory System Design (along with Interconnects)

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      cover image ACM Other conferences
      NoCArc '15: Proceedings of the 8th International Workshop on Network on Chip Architectures
      December 2015
      47 pages
      ISBN:9781450339636
      DOI:10.1145/2835512
      Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 05 December 2015

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      Author Tags

      1. DRAM
      2. Memory systems
      3. interconnects
      4. multi-core
      5. persistent memory
      6. processing in memory
      7. quality of service

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      NoCArc '15 Paper Acceptance Rate 6 of 21 submissions, 29%;
      Overall Acceptance Rate 46 of 122 submissions, 38%

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