skip to main content
research-article

Refined transactional lock elision

Published:27 February 2016Publication History
Skip Abstract Section

Abstract

Transactional lock elision (TLE) is a well-known technique that exploits hardware transactional memory (HTM) to introduce concurrency into lock-based software. It achieves that by attempting to execute a critical section protected by a lock in an atomic hardware transaction, reverting to the lock if these attempts fail. One significant drawback of TLE is that it disables hardware speculation once there is a thread running under lock. In this paper we present two algorithms that rely on existing compiler support for transactional programs and allow threads to speculate concurrently on HTM along with a thread holding the lock. We demonstrate the benefit of our algorithms over TLE and other related approaches with an in-depth analysis of a number of benchmarks and a wide range of workloads, including an AVL tree-based micro-benchmark and ccTSA, a real sequence assembler application.

References

  1. Y. Afek, A. Levy, and A. Morrison. Software-improved hardware lock elision. In Proceedings of ACM PODC, pages 212--221, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Y. Afek, A. Matveev, O. R. Moll, and N. Shavit. Amalgamated lock-elision. In Proceedings of DISC, pages 309--324, 2015.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. J. H. Ahn. ccTSA: A Coverage-Centric Threaded Sequence Assembler. PLoS ONE, 7(6), June 2012. doi: 10.1371/journal.pone.0039232. URL http://dx.doi.org/10.1371/journal.pone.0039232.Google ScholarGoogle Scholar
  4. I. Calciu, T. Shpeisman, G. Pokam, and M. Herlihy. Improved single global lock fallback for best-effort hardware transactional memory. In ACM Workshop on Transactional Computing (TRANSACT), 2014.Google ScholarGoogle Scholar
  5. A. T. Clements, M. F. Kaashoek, and N. Zeldovich. Scalable address spaces using RCU balanced trees. In Proceedings of ASPLOS, pages 199--210, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. L. Dalessandro, M. F. Spear, and M. L. Scott. Norec: Streamlining stm by abolishing ownership records. In Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), pages 67--78, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. L. Dalessandro, F. Carouge, S. White, Y. Lev, M. Moir, M. L. Scott, and M. F. Spear. Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 39--52, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proceedings of ASPLOS, pages 336--346, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proceedings of ASPLOS, pages 157--168, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. D. Dice, Y. Lev, M. Moir, D. Nussbaum, and M. Olszewski. Early experience with a commercial hardware transactional memory implementation. Technical report, Sun Labs, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. D. Dice, T. L. Harris, A. Kogan, Y. Lev, and M. Moir. Pitfalls of lazy subscription. In Workshop on the Theory of Transactional Memory (WTTM), 2014.Google ScholarGoogle Scholar
  12. D. Dice, A. Kogan, Y. Lev, T. Merrifield, and M. Moir. Adaptive integration of hardware and software lock elision techniques. In ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pages 188--197, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. N. Diegues and P. Romano. Self-tuning intel transactional synchronization extensions. In Proceedings of the International Conference on Autonomic Computing (ICAC), pages 209--219, 2014.Google ScholarGoogle Scholar
  14. N. Diegues, P. Romano, and L. Rodrigues. Virtues and limitations of commodity hardware transactional memory. In Proceedings of the International Conference on Parallel Architectures and Compilation (PACT), pages 3--14, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. T. Harris and K. Fraser. Language support for lightweight transactions. In Proceedings of ACM OOPSLA, pages 388--402, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. A. Kleen. TSX anti patterns in lock elision code, Mar. 2014. https://software.intel.com/en-us/articles/tsx-anti-patterns-in-lock-elision-code.Google ScholarGoogle Scholar
  17. A. Matveev and N. Shavit. Reduced hardware lock elision. In Workshop on the Theory of Transactional Memory (WTTM), 2014.Google ScholarGoogle Scholar
  18. A. Matveev and N. Shavit. Reduced hardware NOREC: An opaque obstruction-free and privatizing HyTM. In ACM Workshop on Transactional Computing (TRANSACT), 2014.Google ScholarGoogle Scholar
  19. A. Matveev and N. Shavit. Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory. In Proceedings of ASPLOS, pages 59--71, 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. F. McSherry, M. Isard, and D. G. Murray. Scalability! but at what cost? In Workshop on Hot Topics in Operating Systems (HotOS), 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. T. Nakaike, R. Odaira, M. Gaudet, M. Michael, and H. Tomari. Quantitative Comparison of Hardware Transactional Memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8. In International Symposium on Computer Architecture (ISCA), 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In ACM/IEEE International Symposium on Microarchitecture, pages 294--305, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. T. Riegel, P. Marlier, M. Nowack, P. Felber, and C. Fetzer. Optimizing hybrid transactional memory: The importance of nonspeculative operations. In ACM SPAA, pages 53--64, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. W. Ruan and M. Spear. Hybrid transactional memory revisited. In Proceedings of the International Conference on Distributed Computing (DISC), pages 215--231, 2015.Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. T. Wang. Integer hash function. http://web.archive.org/web/20071223173210/http://www.concentric.net/~Ttwang/tech/inthash.htm, 2007. Accessed: 2015-02-13.Google ScholarGoogle Scholar
  26. R. M. Yoo, C. J. Hughes, K. Lai, and R. Rajwar. Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. In International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Refined transactional lock elision

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 51, Issue 8
        PPoPP '16
        August 2016
        405 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/3016078
        Issue’s Table of Contents
        • cover image ACM Conferences
          PPoPP '16: Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
          February 2016
          420 pages
          ISBN:9781450340922
          DOI:10.1145/2851141

        Copyright © 2016 ACM

        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 27 February 2016

        Check for updates

        Qualifiers

        • research-article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader