Norman P. Jouppi
- 1.Norman P. Jouppi, et. al., "A 300MHz 115W 32b Bipolar ECL Microprocessor," in the IEEE Journal of Solid-State Circuits, November 1993.Google Scholar
- 2.Mark D. Hill, Aspects of Cache Memory and Instruction Buffer Performance, Ph.D. Thesis, University of California Berkeley, 1987. Google ScholarDigital Library
- 3.Ehsan Rashid, et. al., "A CMOS RISC CPU with On-Chip Parallel Cache", in the Proceedings of the 1994 International Solid-State Circuits Conference, pages 210-211.Google Scholar
- 4.Subbarao Palacharla and Richard Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement", in the Proceedings of the 21st International Symposium on Computer Architecture, pages 24-33, April 1994. Google ScholarDigital Library
- 5.Keith Farkas, Norman P. Jouppi, and Paul Chow, "How Useful are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?" in the Proceedings of the 1st Conference on High-Performance Computer Architecture, January, 1995. Google ScholarDigital Library
- 6.Keith Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic, "Memory-System Design Considerations for Dynamically-Scheduled Processors" in the Proceedings of the 24th Annual international Symposium on Computer Architecture, june 1997. Google ScholarDigital Library
- 7.A. J. Smith, "Cache Memories", ACM Computing Surveys, vol. 14, no. 3, pp. 473-530, 1982 Google ScholarDigital Library
Index Terms
- Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
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