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Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression

Published:18 May 2016Publication History
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Abstract

The clock networks of many modern circuits have to operate in multiple corners and multiple modes (MCMM). We propose to construct mode-reconfigurable clock trees (MRCTs) based on mode separation and scenario compression. The technique of scenario compression is proposed to consider the timing constraints in multiple scenarios at the same time, compressing the MCMM problem into an equivalent single-corner multiple-mode (SCMM), or single-corner single-mode (SCSM) problem. The compression is performed by combining the skew constraints of the different scenarios in skew constraint graphs based on delay linearization and dominating skew constraints. An MRCT consists of several clock trees and mode separation involves, depending on the active mode, selecting one of the clock trees to deliver the clock signal. To limit the overhead, the bottom part (closer to the clock sinks) of all the different clock trees are shared and only the top part (closer to the clock source) of the clock network is mode reconfigurable. The reconfiguration is realized using OR-gates and a one-input-multiple-output demultiplexer. The experimental results show that for a set of synthesized MCMM circuits, with 715 to 13, 216 sequential elements, the proposed approach can achieve high yield.

References

  1. Aseem Agarwal, David Blaauw, and Vladimir Zolotov. 2003. Statistical timing analysis for intra-die process variations with spatial correlations. In ICCAD’03. 900--907. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Shashank Bujimalla and Cheng-Kok Koh. 2011. Synthesis of low power clock trees for handling power-supply variations (ISPD’11). 37--44. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, and Siddhartha Nath. 2014. OCV-aware top-level clock tree optimization. In GLSVLSI’14. 33--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Wai Chan Chan. 2009. Process corner estimation circuit with temperature compensation. US Patent 7,634,746.Google ScholarGoogle Scholar
  5. Yong. P. Chen and D. F. Wong. 1996. An algorithm for zero-skew clock tree routing with buffer insertion. In EDTC’96. 230--237. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C.-W. Albert Tsao. 1998. Bounded-skew clock and steiner routing. ACM Trans. Des. Autom. Electron. Syst. 3, 3 (July 1998), 341--388. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Thomas H. Cormen, Clifford Stein, Ronald L. Rivest, and Charles E. Leiserson. 2001. Introduction to Algorithms. McGraw-Hill Higher Education. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Masato Edahiro. 1993. A clustering-based optimization algorithm in zero-skew routings. In DAC. 612--616. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Rickard Ewetz, Shankarshana Janarthanan, and Cheng-Kok Koh. 2014. Fast clock skew scheduling based on sparse-graph algorithms. In ASP-DAC’14. 472--477.Google ScholarGoogle Scholar
  10. Rickard Ewetz, Shankarshana Janarthanan, and Cheng-Kok Koh. 2015. Benchmark circuits for clock scheduling and synthesis. Retrieved from https://purr.purdue.edu/publications/1759.Google ScholarGoogle Scholar
  11. Kwangsoo Han, Andrew B. Kahng, Jongpil Lee, Jiajia Li, and Siddhartha Nath. 2015. A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. In DAC’15. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. International Workshop for Logic Synthesis. 2005. IWLS 2005 Benchmarks. Retrieved from http://iRwls.org/iwls2005/benchmarks.html.Google ScholarGoogle Scholar
  13. Juyeon Kim, Deokjin Joo, and Taewhan Kim. 2013. An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. In DAC’13. 1--6. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Juyeon Kim and Taewhan Kim. 2015. Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. In ASP-DAC’15. 466--471. Google ScholarGoogle ScholarCross RefCross Ref
  15. Dong-Jin Lee and Igor L. Markov. 2011. Multilevel tree fusion for robust clock networks. In ICCAD. 632--639. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Jianchao Lu and Baris. Taskin. 2009. Post-CTS clock skew scheduling with limited delay buffering. In Cir. and Sys. 224--227.Google ScholarGoogle Scholar
  17. NGSPICE. 2012. Homepage. Retrieved from http://ngspice.sourceforge.net/.Google ScholarGoogle Scholar
  18. OpenCores. 2014. Homepage. Retrieved from http://opencores.net/.Google ScholarGoogle Scholar
  19. Anand Rajaram and David Z. Pan. 2011. Robust chip-level clock tree synthesis. In CAD of ICs and Sys. 877--890. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Venky Ramachandran. 2012. Construction of minimal functional skew clock trees. In ISPD’12. 119--120. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David Z. Pan. 2015a. Clock tree resynthesis for multi-corner multi-mode timing closure. In CAD of IC and Sys. 589--602. Google ScholarGoogle ScholarCross RefCross Ref
  22. Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, and Pierre-Olivier Ribet. 2015b. Skew bounded buffer tree resynthesis for clock power optimization. In GLSVLSI’15. 87--90. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, and Jiang Hu. 2010. Useful clock skew optimization under a multi-corner multi-mode design framework. In ISQED’10. 62--68.Google ScholarGoogle Scholar
  24. Mayank Shrivastava and Chaeryung Park. 2014. Compressing scenarios of electronic circuits. US Patent 8,701,063. Retrieved from http://www.google.com/patents/US8701063.Google ScholarGoogle Scholar
  25. Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, and Yeong-Jar Chang. 2010. Clock skew minimization in multi-voltage mode designs using adjustable delay buffers. In CAD of ICs and Sys. 1921--1930. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Cliff N. Sze. 2010. ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. In ISPD’10. 143--143. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Chung-Wen Albert Tsao and Cheng-Kok Koh. 2002. UST/DME: A clock tree router for general skew constraints. ACM Transactions on Design Automation of Electronic Systems (TODAES) 7, 3 (2002), 359--379. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, and Bhuwan Agrawal. 2002. Worst case clock skew under power supply variations. In TAU’02. 22--28. Google ScholarGoogle ScholarDigital LibraryDigital Library

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    • Published in

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 21, Issue 4
      September 2016
      423 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2939671
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents

      Copyright © 2016 ACM

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      New York, NY, United States

      Publication History

      • Published: 18 May 2016
      • Accepted: 1 January 2016
      • Revised: 1 December 2015
      • Received: 1 September 2015
      Published in todaes Volume 21, Issue 4

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