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Effective resource management for enhancing performance of 2D and 3D stencils on GPUs

Published: 12 March 2016 Publication History

Abstract

GPUs are an attractive target for data parallel stencil computations prevalent in scientific computing and image processing applications. Many tiling schemes, such as overlapped tiling and split tiling, have been proposed in past to improve the performance of stencil computations. While effective for 2D stencils, these techniques do not achieve the desired improvements for 3D stencils due to the hardware constraints of GPU.
A major challenge in optimizing stencil computations is to effectively utilize all resources available on the GPU. In this paper we develop a tiling strategy that makes better use of resources like shared memory and register file available on the hardware. We present a systematic methodology to reason about which strategy should be employed for a given stencil and also discuss implementation choices that have a significant effect on the achieved performance. Applying these techniques to various 2D and 3D stencils gives a performance improvement of 200-400% over existing tools that target such computations.

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Cited By

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  • (2024)ConvStencil: Transform Stencil Computation to Matrix Multiplication on Tensor CoresProceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming10.1145/3627535.3638476(333-347)Online publication date: 2-Mar-2024
  • (2023)Revisiting Temporal Blocking Stencil OptimizationsProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593716(251-263)Online publication date: 21-Jun-2023
  • (2023)PERKS: a Locality-Optimized Execution Model for Iterative Memory-bound GPU ApplicationsProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593705(167-179)Online publication date: 21-Jun-2023
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  1. Effective resource management for enhancing performance of 2D and 3D stencils on GPUs

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    cover image ACM Other conferences
    GPGPU '16: Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit
    March 2016
    107 pages
    ISBN:9781450341950
    DOI:10.1145/2884045
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 12 March 2016

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    Author Tags

    1. GPGPU
    2. resource management
    3. stencil computations
    4. tiling

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    PPoPP '16

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    GPGPU '16 Paper Acceptance Rate 9 of 23 submissions, 39%;
    Overall Acceptance Rate 57 of 129 submissions, 44%

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    Cited By

    View all
    • (2024)ConvStencil: Transform Stencil Computation to Matrix Multiplication on Tensor CoresProceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming10.1145/3627535.3638476(333-347)Online publication date: 2-Mar-2024
    • (2023)Revisiting Temporal Blocking Stencil OptimizationsProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593716(251-263)Online publication date: 21-Jun-2023
    • (2023)PERKS: a Locality-Optimized Execution Model for Iterative Memory-bound GPU ApplicationsProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593705(167-179)Online publication date: 21-Jun-2023
    • (2022)Toward accelerated stencil computation by adapting tensor core unit on GPUProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532392(1-12)Online publication date: 28-Jun-2022
    • (2022)An efficient GPU implementation and scaling for higher-order 3D stencilsInformation Sciences: an International Journal10.1016/j.ins.2021.11.042586:C(326-343)Online publication date: 1-Mar-2022
    • (2021)csTuner: Scalable Auto-tuning Framework for Complex Stencil Computation on GPUs2021 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/Cluster48925.2021.00037(192-203)Online publication date: Sep-2021
    • (2021)Adiabatic quantum linear regressionScientific Reports10.1038/s41598-021-01445-611:1Online publication date: 9-Nov-2021
    • (2019)Generating Portable High-Performance Code via Multi-Dimensional HomomorphismsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00035(353-368)Online publication date: 23-Sep-2019
    • (2019)On Optimizing Complex Stencils on GPUs2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2019.00073(641-652)Online publication date: May-2019
    • (2019)An Efficient GPU Implementation Technique for Higher-Order 3D Stencils2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00086(552-561)Online publication date: Aug-2019
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