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CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer

Published: 16 May 2016 Publication History

Abstract

We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep-cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moore's Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines.

References

[1]
R. P. Feynman, "Simulating physics with computers", International journal of theoretical physics, 21(6):467--488, 1982.
[2]
F. R. Braakman, P. Barthelemy, C. Reichl, W. Wegscheider, and L. M. K. Vandersypen, "Long-distance coherent coupling in a quantum dot array," Nat. Nanotechnol. 8, 432--437 (2013).
[3]
E. Kawakami, P. Scarlino, D. R. Ward, F. R. Braakman, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, and L. M. K. Vandersypen, "Electrical control of a long-lived spin qubit in a Si/SiGe quantum dot," Nat. Nanotechnol. 9, 666 (2014).
[4]
D. Kim, Z. Shi, C. B. Simmons, D. R. Ward, J. R. Prance, T. S. Koh, J. K. Gamble, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, and M. A. Eriksson, "Quantum control and process tomography of a semiconductor quantum dot hybrid qubit." Nature 511, 70--4 (2014).
[5]
J. I. Colless, A. C. Mahoney, J. M. Hornibrook, A. C. Doherty, H. Lu, A. C. Gossard, and D. J. Reilly, "Dispersive readout of a few-electron double quantum dot with fast RF gate sensors," Phys. Rev. Lett. 110, 046805 (2013).
[6]
J. I. Colless and D. J. Reilly, "Cryogenic high-frequency readout and control platform for spin qubits," Rev. Sci. Instrum. 83, 023902 (2012).
[7]
R. Kalra, A. Laucht, C. D. Hill, and A. Morello, "Robust two-qubit gates for donors in silicon controlled by hyperfine interactions," Phys. Rev. X. 4, 021044 (2014).
[8]
J. T. Muhonen, J. P. Dehollain, A. Laucht, F. E. Hudson, R. Kalra, T. Sekiguchi, K. M. Itoh, D. N. Jamieson, J. C. McCallum, A. S. Dzurak, and A. Morello, "Storing quantum information for 30 seconds in a nanoelectronic device," Nat. Nanotechnol. 9, 986 (2014).
[9]
J. T. Muhonen, A. Laucht, S. Simmons, J. P. Dehollain, R. Kalra, F. E. Hudson, S. Freer, K. M. Itoh, D. N. Jamieson, J. C. McCallum, A. S. Dzurak, and A. Morello, "Quantifying the quantum gate fidelity of single-atom spin qubits in silicon by randomized benchmarking," J. Phys. Condens. Matter 27, 154205 (2015).
[10]
L. DiCarlo, J. M. Chow, J. M. Gambetta, L. S. Bishop, B. R. Johnson, D. I. Schuster, J. Majer, A. Blais, L. Frunzio, S. M. Girvin, and R. J. Schoelkopf, "Demonstration of two-qubit algorithms with a superconducting quantum processor," Nature 460, 240 (2009).
[11]
D. Risté, S. Poletto, M.-Z. Huang, A. Bruno, V. Vesterinen, O.-P. Saira, and L. DiCarlo, "Detecting bit-flip errors in a logical qubit using stabilizer measurements," Nat. Commun. 6, 6983 (2015).
[12]
R. Barends, J. Kelly, A. Megrant, A. Veitia, D. Sank, E. Jeffrey, T. C. White, J. Mutus, A. G. Fowler, B. Campbell, Y. Chen, Z. Chen, B. Chiaro, A. Dunsworth, C. Neill, P. O'Malley, P. Roushan, A. Vainsencher, J. Wenner, A. N. Korotkov, A. N. Cleland, and J. M. Martinis, "Superconducting quantum circuits at the surface code threshold for fault tolerance," Nature 508, 500 (2014).
[13]
E. Jeffrey, D. Sank, J. Y. Mutus, T. C. White, J. Kelly, R. Barends, Y. Chen, Z. Chen, B. Chiaro, A. Dunsworth, A. Megrant, P. J. J. O'Malley, C. Neill, P. Roushan, A. Vainsencher, J. Wenner, A. N. Cleland, and J. M. Martinis, "Fast accurate state measurement with superconducting qubits," Phys. Rev. Lett. 112, 190504 (2014).
[14]
J. M. Chow, J. M. Gambetta, E. Magesan, D. W. Abraham, A. W. Cross, B. R. Johnson, N. A. Masluk, C. A. Ryan, J. A. Smolin, S. J. Srinivasan, and M. Steffen, "Implementing a strand of a scalable fault-tolerant quantum computing fabric," Nat. Commun. 5, 4015 (2014).
[15]
M. G. Castellano, L. Grönberg, P. Carelli, F. Chiarello, C. Cosmelli, R. Leoni, S. Poletto, G. Torrioli, J. Hassel, and P. Helistö, "Characterization of a fabrication process for the integration of superconducting qubits and rapid-single-flux-quantum circuits," Supercond. Sci. Technol. 19, 860 (2006).
[16]
O. A. Mukhanov, "Energy-efficient single flux quantum technology," IEEE Trans. Appl. Supercond. 21, 760--761 (2011).
[17]
D. R. Ward, D. E. Savage, M. G. Lagally, S. N. Coppersmith, and M. A. Eriksson, "Integration of on-chip field-effect transistor switches with dopantless Si/SiGe quantum dots for high-throughput testing," Appl. Phys. Lett. 102, 213107 (2013).
[18]
H. Al-Taie, L. W. Smith, B. Xu, P. See, J. P. Griffiths, H. E. Beere, G. A. C. Jones, D. A. Ritchie, M. J. Kelly, and C. G. Smith, "Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices," Appl. Phys. Lett. 102, 243102 (2013).
[19]
R. K. Puddy, L. W. Smith, H. Al-Taie, C. H. Chong, I. Farrer, J. P. Griffiths, D. A. Ritchie, M. J. Kelly, M. Pepper, and C. G. Smith, "Multiplexed charge-locking device for large arrays of quantum devices," Appl. Phys. Lett. 107, 143501 (2015).
[20]
A. A. Prager, H. C. George, A. O. Orlov, and G. L. "Experimental demonstration of hybrid cmos-single electron transistor circuits", J. Sci. Technol. B Microelectron. Nanom. Struct. 29, 041004 (2011).
[21]
E. Prati and T. Shinada, "Atomic scale devices: Advancements and directions," in IEEE Int. Electron Devices Meeting (IEDM) pp. 1.2.1--1.2.4 (2014).
[22]
J. Chen, L. Wang, E. Charbon, and B. Wang. Programmable architecture for quantum computing. Phys. Rev. A, 88, 2, 022311 (2013)
[23]
E. Prati, M. De Michielis, M. Belli, S. Cocco, M. Fanciulli, D. Kotekar-Patil, M. Ruoff, D. P. Kern, D. A. Wharam, J. Ver- duijn, G. C. Tettamanzi, S. Rogge, B. Roche, R. Wacquez, X. Jehl, M. Vinet, and M. Sanquer, "Few electron limit of n-type metal oxide semiconductor single electron transistors," Nanotechnology 23, 215204 (2012).
[24]
M. Turchetti, H. Homulle, F. Sebastiano, G. Ferrari, E. Charbon, and E. Prati, "Tunable single hole regime of a silicon field effect transistor in standard CMOS technology," Appl. Phys. Express 9, 014001 (2016).
[25]
J. M. Hornibrook, J. I. Colless, I. D. Conway Lamb, S. J. Pauka, H. Lu, A. C. Gossard, J. D. Watson, G. C. Gardner, S. Fallahi, M. J. Manfra, and D. J. Reilly, "Cryogenic Control Architecture for Large-Scale Quantum Computing," Phys. Rev. Appl. 3, 024010 (2015).
[26]
I. D. Conway Lamb, J. I. Colless, J. M. Hornibrook, S. J. Pauka, S. J. Waddy, M. K. Frechtling, and D. J. Reilly, "A FPGA-based instrumentation platform for use at deep cryogenic temperatures," Rev. Sci. Instrum. 87, 014701 (2016).
[27]
H. Homulle, S. Visser, B. Patra, G. Ferrari, E. Prati, F. Sebastiano, and E. Charbon, "A Reconfigurable Cryogenic Platform for the Classical Control of Scalable Quantum Computers", arXiv:1602.05786v1 (2016).
[28]
K. Das, T. Lehmann, and A. S. Dzurak, "Sub-nanoampere one-shot single electron transistor readout electrometry below 10 Kelvin," IEEE Trans. Circuits Syst. I 61, 2816 (2014).
[29]
B. Murmann, "Digitally Assisted Analog Circuits", IEEE Micro, 26(2), 38--47 (2006).
[30]
J. M. Chow, A. Córcoles, J. M. Gambetta, C. Rigetti, B. Johnson, J. A. Smolin, J. Rozen, G. A. Keefe, M. B. Rothwell, M. B. Ketchen et al., "Simple all-microwave entangling gate for fixed-frequency superconducting qubits," Physical review letters, 107(8), 080502 (2011).
[31]
T. Larsen, K. Petersson, F. Kuemmeth, T. Jespersen, P. Krogstrup, J. Nygard, C. Marcus, "A semiconductor nanowire-based superconducting qubit," arXiv:1503.08339 (2015).
[32]
K. C. Nowack, M. Shafiei, M. Laforest, G. E. D. K. Prawiroatmodjo, L. R. Schreiber, C. Reichl, W. Wegscheider, and L. M. K. Vandersypen, "Single-shot correlations and two-qubit gate of solid-state spins," Science, 333, 6047, 1269--1272 (2011).
[33]
M. Veldhorst, J. Hwang, C. Yang, A. Leenstra, B. de Ronde, J. Dehollain, J. Muhonen, F. Hudson, K. Itoh, A. Morello et al., "An addressable quantum dot qubit with fault-tolerant control-fidelity," Nature nanotechnology, 9(12), 981--985 (2014).
[34]
J. J. Pla, K. Y. Tan, J. P. Dehollain, W. H. Lim, J. J. Morton, F. A. Zwanenburg, D. N. Jamieson, A. S. Dzurak, and A. Morello, "High- fidelity readout and control of a nuclear spin qubit in silicon," Nature 496, 7445, 334--338 (2013).
[35]
J. J. Pla, F. A. Mohiyaddin, K. Y. Tan, J. P. Dehollain, R. Rahman, G. Klimeck, D. N. Jamieson, A. S. Dzurak, and A. Morello, "Coherent control of a single Si 29 nuclear spin qubit," Physical review letters, 113(24), 246801 (2014).
[36]
D. Kim, D. R. Ward, C. B. Simmons, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, "High-fidelity resonant gating of a silicon-based quantum dot hybrid qubit," NPJ Quantum Information, vol. 1, Article number: 15004, 2015.
[37]
Xilinx, "7 series FPGAs overview," (2015).
[38]
C. Favi and E. Charbon, "A 17ps time-to-digital converter implemented in 65nm FPGA technology", in FPGA (ACM Press, New York, New York, USA), 113--120 (2009).
[39]
M. W. Fishburn, H. Menninga, E. Charbon, "A 19.6ps, FPGA-Based TDC with Multiple Channels for Open Source Applications", IEEE Trans. Nuc. Sci., 60(3), 2203--2208 (2013).
[40]
H. Homulle, "Development of a Multichannel TCSPC System in a Spartan 6 FPGA", M.S. thesis, TU Delft (2014).
[41]
H. Homulle, F. Regazzoni, and E. Charbon, "200 MS/s ADC implemented in a FPGA employing TDCs", in FPGA (ACM Press, New York, New York, USA), 228--235 (2015).
[42]
H. Homulle, S. Visser, and E. Charbon, "A 1 GSa/s, Reconfigurable Soft-core FPGA ADC", in FPGA (ACM Press, New York, New York, USA), 281 (2016).
[43]
S. Visser, "A 1 GSa/s Deep Cryogenic, Reconfigurable Soft-core FPGA ADC for Quantum Computing Applications," Master thesis, TU Delft (2015).
[44]
F. Teyssandier and D. Prêle, "Commercially Available Capacitors at Cryogenic Temperatures," Workshop on Low-Temp. Electronics -- WOLTE9 (2010).
[45]
R. Kirschman, "Survey of Low-Temperature Electronics", Workshop on Low-Temp. Electronics WOLTE11 (2014).

Cited By

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  • (2020)Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180666(1-5)Online publication date: Oct-2020
  • (2019)Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETsBalkan Journal of Electrical and Computer Engineering10.17694/bajece.5702157:3(362-365)Online publication date: 30-Jul-2019
  • (2018)Cryo-CMOS Circuits and Systems for Quantum Computing ApplicationsIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.273754953:1(309-321)Online publication date: Jan-2018
  • Show More Cited By
  1. CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer

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      cover image ACM Conferences
      CF '16: Proceedings of the ACM International Conference on Computing Frontiers
      May 2016
      487 pages
      ISBN:9781450341288
      DOI:10.1145/2903150
      • General Chairs:
      • Gianluca Palermo,
      • John Feo,
      • Program Chairs:
      • Antonino Tumeo,
      • Hubertus Franke
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      Publication History

      Published: 16 May 2016

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      Author Tags

      1. (de)coherence
      2. CryoCMOS
      3. cryogenics
      4. error-correcting loop
      5. fault-tolerant computing
      6. quantum computation
      7. quantum micro-architecture
      8. qubit

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      May 16 - 19, 2016
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      CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;
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      View all
      • (2020)Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180666(1-5)Online publication date: Oct-2020
      • (2019)Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETsBalkan Journal of Electrical and Computer Engineering10.17694/bajece.5702157:3(362-365)Online publication date: 30-Jul-2019
      • (2018)Cryo-CMOS Circuits and Systems for Quantum Computing ApplicationsIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.273754953:1(309-321)Online publication date: Jan-2018
      • (2017)Taming the instruction bandwidth of quantum computers via hardware-managed error correctionProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123940(679-691)Online publication date: 14-Oct-2017
      • (2017)Cryo-CMOS Electronic Control for Scalable Quantum ComputingProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3072948(1-6)Online publication date: 18-Jun-2017
      • (2017)Cryogenic CMOS interfaces for quantum devices2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)10.1109/IWASI.2017.7974215(59-62)Online publication date: Jun-2017

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