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LCTES 2016: Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems
ACM2016 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
LCTES'16: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2016 Santa Barbara CA USA June 13 - 14, 2016
ISBN:
978-1-4503-4316-9
Published:
13 June 2016
Sponsors:

Bibliometrics
Abstract

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SESSION: Dynamic Translation and Iterative Compilation
research-article
Efficient asynchronous interrupt handling in a full-system instruction set simulator

Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using ...

research-article
Public Access
Code cache management in managed language VMs to reduce memory consumption for embedded systems

The compiled native code generated by a just-in-time (JIT) compiler in managed language virtual machines (VM) is placed in a region of memory called the code cache. Code cache management (CCM) in a VM is responsible to find and evict methods from the ...

research-article
A graph-based iterative compiler pass selection and phase ordering approach

Nowadays compilers include tens or hundreds of optimization passes, which makes it difficult to find sequences of optimizations that achieve compiled code more optimized than the one obtained using typical compiler options such as -O2 and -O3. The ...

SESSION: Loop and Dataflow Analysis
research-article
Translation validation of loop and arithmetic transformations in the presence of recurrences

Compiler optimization of array-intensive programs involves extensive application of loop transformations and arithmetic transformations. Hence, translation validation of array-intensive programs requires manipulation of intervals of integers (...

research-article
Loop-oriented array- and field-sensitive pointer analysis for automatic SIMD vectorization

Compiler-based auto-vectorization is a promising solution to automatically generate code that makes efficient use of SIMD processors in high performance platforms and embedded systems. Two main auto-vectorization techniques, superword-level parallelism ...

research-article
Generalized cache tiling for dataflow programs

The dataflow programming paradigm has facilitated the expression of a great number of algorithmic applications on embedded platforms in a wide variety of applicative domains. Whether it is a Domain Specific Language (DSL) or a more generalistic one, ...

SESSION: Worst-Case Analysis and Error Handling
research-article
Symbolic execution for memory consumption analysis

With the advances in both hardware and software of embedded systems in the past few years, dynamic memory allocation can now be safely used in embedded software. As a result, the need to develop methods to avoid heap overflow errors in safety-critical ...

research-article
TIC: a scalable model checking based approach to WCET estimation

The application of Model Checking to compute WCET has not been explored as much as Integer Linear Programming (ILP), primarily because model checkers fail to scale for complex programs. These programs have loops with large or unknown bounds, leading to ...

research-article
Compensate or ignore? meeting control robustness requirements through adaptive soft-error handling

To avoid catastrophic events like unrecoverable system failures on mobile and embedded systems caused by soft-errors, software-based error detection and compensation techniques have been proposed. Methods like error-correction codes or redundant ...

SESSION: Computation Partitioning
research-article
Opportunity for compute partitioning in pursuit of energy-efficient systems

Performance of computing systems, from handhelds to supercomputers, is increasingly constrained by the energy consumed. A significant and increasing fraction of the energy is consumed in the movement of data. In a compute node, caches have been very ...

research-article
Public Access
Compiling a gesture recognition application for a low-power spatial architecture

Energy efficiency is one of the main performance goals when designing processors for embedded systems. Typically, the simpler the processor, the less energy it consumes. Thus, an ultra-low power multicore processor will, likely have very small ...

research-article
A machine learning approach to mapping streaming workloads to dynamic multicore processors

Dataflow programming languages facilitate the design of data intensive programs such as streaming applications commonly found in embedded systems. They also expose parallelism that can be exploited using multicore processors which are now part of the ...

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  1. Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems

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    Acceptance Rates

    Overall Acceptance Rate116of438submissions,26%
    YearSubmittedAcceptedRate
    LCTES '14511631%
    LCTES '13601627%
    LCTES '09811822%
    LCTES '031282923%
    LCTES/SCOPES '02732534%
    LCTES '99451227%
    Overall43811626%