Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

Full text

Pdf (1.14 MB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 37 - 46

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Alexander (Sandy) Marquardt	Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4
Vaughn Betz	Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4
Jonathan Rose	Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 51, Citation Count: 30

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/296399.296426 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Alte98	Altera Inc., Data Book, 1998.
	Betz97a	V. Betz and J. Rose, "Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size," IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1997, pp. 551-554.
	Betz97b	Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
	Betz98a	Vaughn Betz , Jonathan Rose, How Much Logic Should Go in an FPGA Logic Block?, IEEE Design & Test, v.15 n.1, p.10-15, January 1998 [doi>10.1109/54.655177 ]
	Betz98b	V. Betz, "Architecture and CAD for Speed and Area Optimization of FPGAs;' Ph.D. Dissertation, University of Toronto, 1998.
	Betz98c	V. Betz, "VPR and VPack User's Manual (Version 4.17)," May 5, 1998. (Available for download from http : //www. e ec g. toronto, edu/~ vau g hnA,pr/vp r. htrnl ).
	Betz99	Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
	Brow92	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	Brow96	Stephen Brown , Jonathan Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design & Test, v.13 n.2, p.42-57, June 1996 [doi>10.1109/54.500200 ]
	Cong94	J. Cong and Y. Ding, "Flowmap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on CAD, Jan. 1994, pp I- 12.
	Elmo48	W.C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers;' J. Applied Physics, Vol. 19, January 1948, pp. 55-63.
	Fran92	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	Gall98	D. Galloway, "Implementation of Grayscale Conversion for Video Image Processing on the Transmogrifier-2a," Personal Communication.
	Hame98	I. Hamer, "Implementation of DES on the Transmogrifier-2a," Personal Communication.
	Hitc83	R. Hitchcock, G. Smith and D. Cheng, "Timing Analysis of Computer-Hardware" IBM Journal of Research and Development, Jan. 1983, pp. 100 - 105.
	Leve98	P. Leventis, "Using edif2blif Version 1.0" June 30, 1998. (Available for download from hnp:// www. eecg. toronto, edu/-leventi/edif2blif/ edif2blif, html).
	Luce98	Lucent Technologies, FPGA Data Book, 1998
	Meta92	Meta-Software, Hspice User's Manual, 1992.
	Padi98	K. Padalia, "Implementation of Grayscale Conversion for Video Image Processing on the Transmogrifier-2a," Personal Communication.
	Rose90	J. Rose, R. J. Francis, D. Lewis and P. Chow, "Architecture of Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE Journal of Solid State Circuits, Oct. 1990, pp. 1217 - 1225.
	Rose91	J. Rose and S. Brown. "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," JSSC, March 1991, pp. 277 - 282.
	Rose93	J. Rose, A. El Gamal and A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays;' Proceedings IEEE, vol. 81, no. 7, July 1993, pp. l 013 - I029.
	Sent92	E.M. Sentovich et al, "SIS: A System for Sequential Circuit Analysis" Tech. Report No. UCB/ERL M92/41, University of California, Berkeley, 1992.
	Swar98	Jordan S. Swartz , Vaughn Betz , Jonathan Rose, A fast routability-driven router for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.140-149, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275134]
	Vant98	Vantis Corporation, "VF1 Field Programmable Gate Array," Preliminary Data Sheet, 1998.
	West93	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	Xili94	Xilinx Inc., The Programmable Logic Data Book, 1994.
	Xili97	Xilinx Inc., "XC5200 Series of FPGAs", Data Book, 1997.
	Xili98	Xilinx Inc., ':Virtex 2.5 V Field Programmable Gate Arrays", Advance Product Data Sheet, 1998.
	Yang91	S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0" Tech. Report, Microelectronics Center of North Carolina, 1991.
	Ye98	A. Ye, "Procedural Texture Mapping on FPGAs", M.A.Sc. Thesis, in Preparation, 1998.

CITED BY 30

	Jason Cong , Songjie Xu, Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs, Proceedings of the 2000 conference on Asia South Pacific design automation, p.157-162, January 2000, Yokohama, Japan
	Marrakchi Zied , Mrabet Hayder , Amouri Emna , Mehrez Habib, Efficient tree topology for FPGA interconnect network, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Elaheh Bozorgzadeh , Seda Ogrenci-Memik , Majid Sarrafzadeh, RPack: routability-driven packing for cluster-based FPGAs, Proceedings of the 2001 conference on Asia South Pacific design automation, p.629-634, January 2001, Yokohama, Japan
	Chetan Patel , Anthony Cozzie , Herman Schmit , Larry Pileggi, An architectural exploration of via patterned gate arrays, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Chang Woo Kang , Massoud Pedram, Clustering techniques for coarse-grained, antifuse FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Cristinel Ababei , Hushrav Mogal , Kia Bazargan, Three-dimensional place and route for FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Vivek Garg , Vikram Chandrasekhar , M. Sashikanth , V. Kamakoti, A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Chang Woo Kang , Massoud Pedram, Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Hassan Hassan , Mohab Anis , Antoine El Daher , Mohamed Elmasry, Activity Packing in FPGAs for Leakage Power Reduction, Proceedings of the conference on Design, Automation and Test in Europe, p.212-217, March 07-11, 2005
	Julien Lamoureux , Steven J. E. Wilton, On the Interaction Between Power-Aware FPGA CAD Algorithms, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.701, November 09-13, 2003
	Mike Sheng , Jonathan Rose, Mixing buffers and pass transistors in FPGA routing architectures, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.75-84, February 2001, Monterey, California, United States
	Karl Schabas , Stephen D. Brown, Using logic duplication to improve performance in FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Gang Chen , Jason Cong, Simultaneous timing-driven placement and duplication, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Yajun Ran , M. Marek-Sadowska, An integrated design flow for a via-configurable gate array, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.582-589, November 07-11, 2004
	Guy Lemieux , David Lewis, Using sparse crossbars within LUT, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.59-68, February 2001, Monterey, California, United States
	Tim (Tianming) Kong, A novel net weighting algorithm for timing-driven placement, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.172-176, November 10-14, 2002, San Jose, California
	Gang Chen , Jason Cong, Simultaneous placement with clustering and duplication, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.740-772, July 2006
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev, Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Taneem Ahmed , Paul D. Kundarewich , Jason H. Anderson , Brad L. Taylor , Rajat Aggarwal, Architecture-specific packing for virtex-5 FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Vaughn Betz , Jonathan Rose, Automatic generation of FPGA routing architectures from high-level descriptions, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.175-184, February 10-11, 2000, Monterey, California, United States
	Hassan Hassan , Mohab Anis , Mohamed Elmasry, LAP: a logic activity packing methodology for leakage power-tolerant FPGAs, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Elias Ahmed , Jonathan Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.3-12, February 10-11, 2000, Monterey, California, United States
	Wei Zhang , Li Shang , Niraj K. Jha, NanoMap: an integrated design optimization flow for a hybrid nanotube/CMOS dynamically reconfigurable architecture, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Interconnect resource-aware placement for hierarchical FPGAs, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Joey Y. Lin , Deming Chen , Jason Cong, Optimal simultaneous mapping and clustering for FPGA delay optimization, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Amit Singh , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Yajun Ran , Malgorzata Marek-Sadowska, Via-configurable routing architectures and fast design mappability estimation for regular fabrics, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.9, p.998-1009, September 2006
	Ian Kuon , Jonathan Rose, Area and delay trade-offs in the circuit and architecture design of FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Peter Hallschmid , Steve J. E. Wilton, Routing architecture optimizations for high-density embedded programmable IP cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1320-1324, November 2005