Florent de Dinechin
ABSTRACT
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Index Terms
- Towards adaptable hierarchical placement for FPGAs
Recommendations
Improved placement for hierarchical FPGAs exploiting local interconnect resources
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the DunesThe majority of networks subject to routing in almost every FPGA design consist of networks with only 2 to 4 terminals. These usually connect to directly adjacent logic cells. In order to make best use of this circumstance commercial FPGA architecture ...
Towards scalable placement for FPGAs
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysPlacement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity to the order of 100K LUTs, the long runtime associated with simulated ...
Routing-architecture-aware analytical placement for heterogeneous FPGAs
DAC '15: Proceedings of the 52nd Annual Design Automation ConferencePlacement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed ...
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