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POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip

Published: 11 September 2016 Publication History

Abstract

Reducing static NoC power consumption is becoming critical for energy-efficient computing as technology scales down since NoCs are devouring a large fraction of the on-chip power budget. We propose Fly-Over (FLOV), a light-weight distributed mechanism for power-gating routers. With simple modifications to the baseline router architecture, FLOV links are facilitated over power-gated routers. A Handshake protocol that allows seamless router power-gating in addition to a dynamic routing algorithm, that provides best-effort minimal path without the necessity for global network information, maintain normal NoC functionality. We evaluate our schemes using synthetic workloads as well as real workloads from PARSEC 2.1 benchmark suite. The results show that FLOV can achieve on average 19.2% latency reduction and 15.9% total energy savings.

References

[1]
N. Jiang, D. U. Becker, G. Michelogiannakis, J. Balfour, B. Towles, D. E. Shaw, J.-H. Kim, and W. J. Dally. A Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator. In International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 86--96. IEEE, 2013.
[2]
A. Samih, R. Wang, A. Krishna, C. Maciocco, C. Tai, and Y. Solihin. Energy-Efficient Interconnect via Router Parking. In International Symposium on High Performance Computer Architecture (HPCA), pages 508--519. IEEE, 2013.

Cited By

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  • (2021)Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark SiliconIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300755540:4(633-645)Online publication date: Apr-2021
  • (2021)A Voting Approach for Adaptive Network-on-Chip Power-GatingIEEE Transactions on Computers10.1109/TC.2020.303316370:11(1962-1975)Online publication date: 1-Nov-2021
  • (2019)Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnectsIET Computers & Digital Techniques10.1049/iet-cdt.2019.0039Online publication date: 18-Jun-2019
  • Show More Cited By

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Published In

cover image ACM Conferences
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
September 2016
474 pages
ISBN:9781450341219
DOI:10.1145/2967938
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2016

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Author Tags

  1. networks-on-chip
  2. power-gating

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PACT '16
Sponsor:
  • IFIP WG 10.3
  • IEEE TCCA
  • SIGARCH
  • IEEE CS TCPP

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PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;
Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

View all
  • (2021)Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark SiliconIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300755540:4(633-645)Online publication date: Apr-2021
  • (2021)A Voting Approach for Adaptive Network-on-Chip Power-GatingIEEE Transactions on Computers10.1109/TC.2020.303316370:11(1962-1975)Online publication date: 1-Nov-2021
  • (2019)Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnectsIET Computers & Digital Techniques10.1049/iet-cdt.2019.0039Online publication date: 18-Jun-2019
  • (2018)Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon2018 8th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2018.8704027(74-79)Online publication date: Dec-2018

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