ABSTRACT
In the majority of safety critical systems, suspension-based locking protocols e.g. MPCP, OMLP, FMLP are used to efficiently and safely coordinate accesses to shared resources. However, existing architectures do not support such arbitration for Networks-on-Chip (NoCs) although they must resolve conflicts between concurrent transmissions. Enabling suspensions requires not only predictable transmission latencies but also to provide feedback about the global state of the interconnect which is difficult in NoCs where arbitration is done locally and independently in routers. This leads to pessimistic formal guarantees, decreased utilization and unfulfilled design requirements as network blocking unnecessarily propagates to other tasks scheduled on cores. In this work, we evaluate existing NoC architectures and propose extensions allowing to benefit from real-time tasks multithreading to increase performance while achieving predictability. Consequently, we describe how to improve the processor's utilization and more importantly, how to consistently reach lower worst case latencies for other tasks running in the system. We demonstrate the effectiveness of our approach using formal analysis and scenario-based simulation results.
- R. Rajkumar, Synchronization in Real-Time Systems: A Priority Inheritance Approach. Norwell, MA, USA: Kluwer Academic Publishers, 1991. Google ScholarDigital Library
- B. B. Brandenburg and J. H. Anderson, "The omlp family of optimal multiprocessor real-time locking protocols," Des. Autom. Embedded Syst., vol. 17, pp. 277--342, June 2013. Google ScholarDigital Library
- A. Block, H. Leontyev, B. B. Brandenburg, and J. H. Anderson, "A flexible real-time locking protocol for multiprocessors," in RTCSA, pp. 47--56, Aug 2007. Google ScholarDigital Library
- K. Goossens and A. Hansson, "The aethereal network on chip after ten years: Goals, evolution, lessons, and future," in DAC, pp. 306--311, June 2010. Google ScholarDigital Library
- A. Burns, L. S. Indrusiak, and Z. Shi, "Schedulability analysis for real time on-chip communication with wormhole switching," Int. J. Embed. Real-Time Commun. Syst., vol. 1, pp. 1--22, Apr. 2010. Google ScholarDigital Library
- A. Kostrzewa, S. Saidi, L. Ecco, and R. Ernst, "Dynamic admission control for real-time networks-on-chips," in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 719--724, Jan 2016.Google Scholar
- H. M. G. Wassel, Y. Gao, J. K. Oberg, T. Huffmire, R. Kastner, F. T. Chong, and T. Sherwood, "Surfnoc: A low latency and provably non-interfering approach to secure networks-on-chip," 2013.Google Scholar
- A. Kostrzewa, S. Saidi, and R. Ernst, "Dynamic control for mixed-critical networks-on-chip," in Real-Time Systems Symposium, 2015 IEEE, pp. 317--326, Dec 2015. Google ScholarDigital Library
- M. Bekooij, R. Hoes, O. Moreira, P. Poplavko, M. Pastrnak, B. Mesman, J. D. Mol, S. Stuijk, V. Gheorghita, and J. Van Meerbergen, "Dataflow analysis for real-time embedded multiprocessor system design," in Dynamic and robust streaming in and between connected consumer-electronic devices, pp. 81--108, Springer Netherlands, 2005.Google Scholar
- L. S. Indrusiak, "End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration," Journal of Systems Architecture, vol. 60, no. 7, pp. 553--561, 2014.Google ScholarCross Ref
- Y. Qian, Z. Lu, and W. Dou, "Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip," in Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on, pp. 44--53, May 2009. Google ScholarDigital Library
- J. Diemer and et al., "Real-time communication analysis for networks with two-stage arbitration," in EMSOFT, (New York, NY, USA), pp. 243--252, ACM, 2011. Google ScholarDigital Library
- OSEK Group, "OSEK/VDX Operating System Specification," 2015.Google Scholar
- S. Schliecker, M. Negrean, and R. Ernst, "Response time analysis on multicore ecus with shared resources," IEEE Transactions on Industrial Informatics, vol. 5, pp. 402--413, Nov 2009.Google ScholarCross Ref
- H. M. G. Wassel, Y. Gao, J. K. Oberg, T. Huffmire, R. Kastner, F. T. Chong, and T. Sherwood, "Surfnoc: A low latency and provably non-interfering approach to secure networks-on-chip," in ISCA, 2013. Google ScholarDigital Library
- A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, "Phasenoc: Tdm scheduling at the virtual-channel level for efficient network traffic isolation," in DATE, 2015. Google ScholarDigital Library
- E. Bolotin and et al., "Qnoc: Qos architecture and design process for network on chip," JOURNAL OF SYSTEMS ARCHITECTURE, 2004. Google ScholarDigital Library
- W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003. Google ScholarDigital Library
- A. Burns, J. Harbin, and L. Indrusiak, "A wormhole noc protocol for mixed criticality systems," in Real-Time Systems Symposium (RTSS), 2014 IEEE, pp. 184--195, Dec 2014.Google Scholar
- I. Walter, I. Cidon, R. Ginosar, and A. Kolodny, "Access regulation to hot-modules in wormhole nocs," in NOCS, pp. 137--148, May 2007. Google ScholarDigital Library
- R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst, "System level performance analysis - the symta/s approach," in IEE Proceedings Computers and Digital Techniques, 2005.Google Scholar
- S. Schliecker and et al, "Providing accurate event models for the analysis of heterogeneous multiprocessor systems," in CODES+ISSS, pp. 185--190, ACM, 2008. Google ScholarDigital Library
- R. Racu and et al, "Improved response time analysis of tasks scheduled under preemptive round-robin," in CODES+ISSS, pp. 179--184, ACM, 2007. Google ScholarDigital Library
- J. Diemer, P. Axer, and R. Ernst, "Compositional performance analysis in python with pycpa," in WATERS, jul 2012.Google Scholar
- R. Pellizzoni, P. Meredith, M.-Y. Nam, M. Sun, M. Caccamo, and L. Sha, "Handling mixed-criticality in soc-based real-time embedded systems," in EMSOFT, ACM, 2009. Google ScholarDigital Library
- Y. H. et al., "Proposal and quantitative analysis of the chstone benchmark program suite for practical c-based high-level synthesis," Journal of Information Processing, vol. 17, pp. 242--254, 2009.Google ScholarCross Ref
- S. Baruah and B. Chattopadhyay, "Response-time analysis of mixed criticality systems with pessimistic frequency specification," in Embedded and Real-Time Computing Systems and Applications (RTCSA), 2013 IEEE 19th International Conference on, pp. 237--246, Aug 2013.Google Scholar
Recommendations
Triplet-based topology for on-chip networks
Most CMPs use on-chip network to connect cores and tend to integrate more simple cores on a single die. As the number of cores increases, on-chip network will play an important role in the performance of future CMPs. Due to the tradeoff between the ...
A Real-Time Locking Protocol
The authors examine a priority driven two-phase lock protocol called the read/write priority ceiling protocol. It is shown that this protocol leads to freedom from mutual deadlock. In addition, a high-priority transactions can be blocked by lower ...
Comments