- 1.M.R. Stan and W.P. Burleson, "Low-Power Eocodings for Global Communication in CMOS VLSL" IEEE Trans. on VLSI Systems, Vol 5, No. 4, Dec. 1997, pp. 444- 455. Google ScholarDigital Library
- 2.S. Ramprasad, N.R. Shanbhag, I.N. Hajj, "Signal Coding for Low Power. Fundamental limits and Practical Realizations," ISCAS98:1998 Int. Syrup. on Circuits and Systema, Monterey, CA 1998.Google Scholar
- 3.P.R. Panda, N. D. Dutt, "'Reducing Address Bus Transitions for Low Power Memory Mapping," EDTC,96: IEEE European Design and Test Conference, pp. 63-67, Paris, France, March 1996. Google ScholarDigital Library
- 4.M.R. Start, W. P. Butte.son, "Bus-Invert Coding for Low Power I/O," IEEETram. on VLSISystems, Vol. 3, No.l, pp.49-58, Mar. 1995. Google ScholarDigital Library
- 5.C.L. Su, C. Y. Tsni, A. M. Despain, "Saving Power in the Control Path of Embedded Processors," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 24-30, Winter 1994. Google ScholarDigital Library
- 6.H. Mehta, R. M. Owens, M. J. Irwin, "Some Issues in Gray Code Addressing," GLS-VI_,SI-96: IEEE 6th Great Lakes Symposium on V/-SL pp. 178-180, Ames, IA, Mar. 1996. Google ScholarDigital Library
- 7.L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, "Address Bus Encoding Techniques for System-Level Power Optimization," DATE 98: }EEE Design Automation and Test in Europe, Paris 1998. Google ScholarDigital Library
- 8.L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer, "Power Optimization od Coie-Based Systems by Address Bus Encoding," IEEE Trans. on VLSI Systems, VoL 6, No. 4, Dec. 98, pp. 554-562. Google ScholarDigital Library
- 9.E. Musoll, T. Iamg, J. Cortadella, "Working-Zone Encoding for Reducing the Enrgy in Microprocessor Address Buses',, IEE Trans. on VLSl SYstems, Vol. 6, No.4, dec. 98, pp.568-572. Google ScholarDigital Library
- 10.C.L. Su and A.M. Despain, "Cache Design Trade-offs for Power and Performance Optimization: A Case Study," ISLPED95, Int. Syrup. on Low Power Design, Monterey, CA 1995. Google ScholarDigital Library
- 11.Y. Li and J. HenkeL "A Framework for Estimating and Minimizing Eneagy Dissipation of Embedded HW/SW Systems," 1998 ACM/IEEE Design Automation Conference. Jun. 98. Google ScholarDigital Library
- 12.J. L. Hennessy and D.A. Patterson, Computer Architeture: A Quantitative Approach, 2m Ed., Morgan Kaufmann, 1996 Google ScholarDigital Library
- 13.C.Silvano, "Power Estimation and Optimization Methdologies for Digital Circuits And Systems", Ph.D. Thesis, University of Brescia, Italy, Dec. 1998.Google Scholar
- 14.P. Hicks, M. Walmmk, R.M. Owens, "Analysis of Power Consumption in Memory Hierarchies", ISLPED-97:1997 Int. Syrnp. on Low Power Elect. and Desigtg Monterey, CA, Aug. 97, pp. 239-242. Google ScholarDigital Library
Index Terms
- Power estimation for architectural exploration of HW/SW communication on system-level buses
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