skip to main content
research-article

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Published:23 May 2017Publication History
Skip Abstract Section

Abstract

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

References

  1. A. Alsuwaiyan and K. Mohanram. 2015. MFNW: A flip-n-write architecture for multi-level cell non-volatile memories. In 2015 IEEE/ACM International Symposium on Nanoscale Architectures. 13--18. DOI:http://dx.doi.org/10.1109/NANOARCH.2015.7180577 Google ScholarGoogle ScholarCross RefCross Ref
  2. S. Di Carlo, S. Galfano, M. Indaco, P. Prinetto, D. Bertozzi, P. Olivo, and C. Zambelli. 2014. FLARES: An aging aware algorithm to autonomously adapt the error correction capability in NAND flash memories. ACM Trans. Archit. Code Optim. 11, 3 (Oct. 2014), 26--50. DOI:http://dx.doi.org/10.1145/2631919 Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C.-H. Chen, P.-C. Hsiu, T.-W. Kuo, C.-L. Yang, and C.-Y. Michael Wang. 2012. Age-based PCM wear leveling with nearly zero search cost. In 2012 Proceedings of the 49th Annual Design Automation Conference. 453--458. DOI:http://dx.doi.org/10.1145/2228360.2228439 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. S. Chen, P. B. Gibbons, and S. Nath. 2011. Rethinking database algorithms for phase change memory. In 2011 5th Biennial Conference on Innovative Data Systems Research. 21--31.Google ScholarGoogle Scholar
  5. S. Cho and H. Lee. 2009. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 347--357. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Y. Choi, I. Song, M. H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. G. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y. J. Lee, Q. Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y. T. Lee, J. Yoo, and G. Jeong. 2012. A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. In 2012 IEEE International Solid-State Circuits Conference. 46--48. DOI:http://dx.doi.org/10.1109/ISSCC.2012.6176872 Google ScholarGoogle ScholarCross RefCross Ref
  7. X. Dong and Y. Xie. 2011. AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. In 2011 16th Asia and South Pacific Design Automation Conference. 31--36. DOI:http://dx.doi.org/10.1109/ASPDAC.2011.5722206 Google ScholarGoogle ScholarCross RefCross Ref
  8. Y. Du, M. Zhou, B. R. Childers, D. Mossé, and R. Melhem. 2013. Bit mapping for balanced PCM cell programming. In 2013 40th Annual International Symposium on Computer Architecture. 428--439. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. G. D. Forney. 1988a. Coset codes. I. introduction and geometrical classification. IEEE Trans. Inf. Theory 34, 5 (Sep. 1988), 1123--1151. DOI:http://dx.doi.org/10.1109/18.21245 Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. G. D. Forney. 1988b. Coset codes. II. Binary lattices and related codes. IEEE Trans. Inf. Theory 34, 5 (Sep. 1988), 1152--1187. DOI:http://dx.doi.org/10.1109/18.21246 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. J. Han, J. Pei, and Y. Yin. 2000. Mining frequent patterns without candidate generation. SIGMOD Rec. 29, 2 (May 2000), 1--12. DOI:http://dx.doi.org/10.1145/335191.335372 Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. M. Han and Y. Han. 2016. Bit flip reduction schemes to improve PCM lifetime: A survey. IEIE Trans. Smart Process. Comput. 5, 5 (Oct. 2016), 337--345. Google ScholarGoogle ScholarCross RefCross Ref
  13. I. Heng and C. H. Cooke. 1998. Error correcting codes associated with complex hadamard matrices. Appl. Math. Lett. 11, 4 (July 1998), 77--80. DOI:http://dx.doi.org/10.1016/S0893-9659(98)00059-7 Google ScholarGoogle ScholarCross RefCross Ref
  14. A. N. Jacobvitz, R. Calderbank, and D. J. Sorin. 2013. Coset coding to extend the lifetime of memory. In 2013 IEEE 19th International Symposium on High Performance Computer Architecture. 222--233. DOI:http://dx.doi.org/10.1109/HPCA.2013.6522321 Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. L. Jiang, Y. Zhang, and J. Yang. 2014. Mitigating write disturbance in super-dense phase change memories. In 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. 216--227. DOI:http://dx.doi.org/10.1109/DSN.2014.32 Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. H. A. Khouzani, C. Yang, and Jingtong Hu. 2015. Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy. In 2015 20th Asia and South Pacific Design Automation Conference. 508--513. DOI:http://dx.doi.org/10.1109/ASPDAC.2015.7059057 Google ScholarGoogle ScholarCross RefCross Ref
  17. D. H. Lawrie. 1975. Access and alignment of data in an array processor. IEEE Trans. Comput. 24, 12 (Dec. 1975), 1145--1155. DOI:http://dx.doi.org/10.1109/T-C.1975.224157 Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. 2009. Architecting phase change memory as a scalable dram alternative. SIGARCH Comput. Archit. News 37, 3 (June 2009), 2--13. DOI:http://dx.doi.org/10.1145/1555815.1555758 Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. S. Li and T. Zhang. 2009. Tri-level-cell phase change memory: Toward an efficient and reliable memory system. In 2009 19th ACM Great Lakes Symposium on VLSI. 499--504. DOI:http://dx.doi.org/10.1145/1531542.1531655 Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Y. Lin, P.-C. Huang, D. Liu, X. Zhu, and L. Liang. 2016. Making in-memory frequent pattern mining durable and energy efficient. In 2016 45th International Conference on Parallel Processing. Google ScholarGoogle ScholarCross RefCross Ref
  21. D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge, and E. H. M. Sha. 2014. Application-specific wear leveling for extending lifetime of phase change memory in embedded systems. IEEE Trans. Comput-Aid. Design Integr. Circuits Syst. 33, 10 (Oct. 2014), 1450--1462. DOI:http://dx.doi.org/10.1109/TCAD.2014.2341922 Google ScholarGoogle ScholarCross RefCross Ref
  22. D. Liu, K. Zhong, T. Wang, Y. Wang, Z. Shao, E. Sha, and J. Xue. 2016. Durable address translation in PCM-based flash storage systems. IEEE Trans. Parallel Distrib. Syst PP, 99 (2016), 1--1. DOI:http://dx.doi.org/10.1109/TPDS.2016.2586059 Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. R. Maddah, S. M. Seyedzadeh, and R. Melhem. 2015. CAFO: Cost aware flip optimization for asymmetric memories. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture. 320--330. DOI:http://dx.doi.org/10.1109/HPCA.2015.7056043 Google ScholarGoogle ScholarCross RefCross Ref
  24. P. Mangalagiri, K. Sarpatwari, A. Yanamandra, V. Narayanan, Y. Xie, M. J. Irwin, and O. A. Karim. 2008. A low-power phase change memory based hybrid cache architecture. In 2008 18th ACM Great Lakes Symposium on VLSI. 395--398. DOI:http://dx.doi.org/10.1145/1366110.1366204 Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. J. Massey. 1965. Step-by-step decoding of the bose-chaudhuri-hocquenghem codes. IEEE Trans. Inf. Theory 11, 4 (Oct. 1965), 580--585. DOI:http://dx.doi.org/10.1109/TIT.1965.1053833 Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. R. Micheloni, A. Marelli, and R. Ravasio. 2010. Error Correction Codes for Non-Volatile Memories. Springer Publishing Company.Google ScholarGoogle Scholar
  27. NanGate 2008. Nangate 45nm Open Cell Library. NanGate. Retrieved from http://www.nangate.com/?pageid=2325.Google ScholarGoogle Scholar
  28. A. Phansalkar, A. Joshi, and L. K. John. 2007. Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. In 2007 34th Annual International Symposium on Computer Architecture. 412--423. DOI:http://dx.doi.org/10.1145/1250662.1250713 Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. 2009. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 14--23.Google ScholarGoogle Scholar
  30. P. Rosenfeld, E. Cooper-Balis, and B. Jacob. 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE Comput. Arch. Lett. 10, 1 (Jan. 2011), 16--19. DOI:http://dx.doi.org/10.1109/L-CA.2011.4 Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. S. Schechter, G. H. Loh, K. Straus, and D. Burger. 2010. Use ECP, not ECC, for hard failures in resistive memories. In 2010 37th Annual International Symposium on Computer Architecture. 141--152. DOI:http://dx.doi.org/10.1145/1815961.1815980 Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H. H. S. Lee. 2010. SAFER: Stuck-at-fault error recovery for memories. In 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture. 115--124. DOI:http://dx.doi.org/10.1109/MICRO.2010.46 Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Synopsys 2010. Design Compiler User Guide. Retrieved from http://acsweb.ucsd.edu/coz004/DC_user_guide.pdf.Google ScholarGoogle Scholar
  34. Synopsys 2016. PrimeTime Golden Timing Signoff Solution and Environment. Retrieved from https://www.synopsys.com/Tools/Implementation/SignOff/Documents/primetime_ds.pdf.Google ScholarGoogle Scholar
  35. J. Wang, X. Dong, G. Sun, D. Niu, and Y. Xie. 2012. Energy-efficient multi-level cell phase-change memory system with data encoding. In 2011 29th IEEE Conference on Computer Design. 175--182. DOI:http://dx.doi.org/10.1109/ICCD.2011.6081394 Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. R. Wang, L. Jiang, Y. Zhang, and J. Yang. 2015. SD-PCM: Constructing reliable super dense phase change memory under write disturbance. In 2015 20th International Conference on Architectural Support for Programming Languages and Operating Systems. 19--31. DOI:http://dx.doi.org/10.1145/2694344.2694352 Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. W. Xu, J. Liu, and T. Zhang. 2009. Data manipulation techniques to reduce phase change memory write energy. In 2009 Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design. 237--242. DOI:http://dx.doi.org/10.1145/1594233.1594290 Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. B.-D. Yang, J.-E. Lee, J.-S. Kim, J. Cho, S.-Y. Lee, and B. gon Yu. 2007. A low power phase-change random access memory using a data-comparison write scheme. In 2007 IEEE International Symposium on Circuits and Systems. 3014--3017. DOI:http://dx.doi.org/10.1109/ISCAS.2007.377981 Google ScholarGoogle ScholarCross RefCross Ref
  39. D. H. Yoon, J. Chang, R. S. Schreiber, and N. P. Jouppi. 2013. Practical nonvolatile multilevel-cell phase change memory. In 2013 International Conference for High Performance Computing, Networking, Storage and Analysis. 1--12. DOI:http://dx.doi.org/10.1145/2503210.2503221 Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez. 2011. FREE-p: Protecting non-volatile memory against both hard and soft errors. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture. 466--477. DOI:http://dx.doi.org/10.1109/HPCA.2011.5749752 Google ScholarGoogle ScholarCross RefCross Ref
  41. P. Zhou, B. Zhao, J. Yang, and Y. Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. SIGARCH Comput. Archit. News 37, 3 (June 2009), 14--23. DOI:http://dx.doi.org/10.1145/1555815.1555759 Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Content-Aware Bit Shuffling for Maximizing PCM Endurance

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        • Published in

          cover image ACM Transactions on Design Automation of Electronic Systems
          ACM Transactions on Design Automation of Electronic Systems  Volume 22, Issue 3
          July 2017
          440 pages
          ISSN:1084-4309
          EISSN:1557-7309
          DOI:10.1145/3062395
          • Editor:
          • Naehyuck Chang
          Issue’s Table of Contents

          Copyright © 2017 ACM

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 23 May 2017
          • Accepted: 1 November 2016
          • Revised: 1 October 2016
          • Received: 1 June 2016
          Published in todaes Volume 22, Issue 3

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • research-article
          • Research
          • Refereed

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader