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P3ARSEC: towards parallel patterns benchmarking

Published: 03 April 2017 Publication History

Abstract

High-level parallel programming is a de-facto standard approach to develop parallel software with reduced time to development. High-level abstractions are provided by existing frameworks as pragma-based annotations in the source code, or through pre-built parallel patterns that recur frequently in parallel algorithms, and that can be easily instantiated by the programmer to add a structure to the development of parallel software. In this paper we focus on this second approach and we propose P3ARSEC, a benchmark suite for parallel pattern-based frameworks consisting of a representative subset of PARSEC applications. We analyse the programmability advantages and the potential performance penalty of using such high-level methodology with respect to hand-made parallelisations using low-level mechanisms. The results are obtained on the new Intel Knights Landing multicore, and show a significantly reduced code complexity with comparable performance.

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cover image ACM Conferences
SAC '17: Proceedings of the Symposium on Applied Computing
April 2017
2004 pages
ISBN:9781450344869
DOI:10.1145/3019612
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 April 2017

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Author Tags

  1. Intel KNL
  2. PARSEC benchmarks
  3. parallel patterns

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  • Research-article

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SAC 2017
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SAC 2017: Symposium on Applied Computing
April 3 - 7, 2017
Marrakech, Morocco

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Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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  • (2020)A Methodology Approach to Compare Performance of Parallel Programming Models for Shared-Memory ArchitecturesNumerical Computations: Theory and Algorithms10.1007/978-3-030-39081-5_28(318-325)Online publication date: 14-Feb-2020
  • (2019)High-Level and Productive Stream Parallelism for Dedup, Ferret, and Bzip2International Journal of Parallel Programming10.1007/s10766-018-0558-x47:2(253-271)Online publication date: 1-Apr-2019
  • (2019)PAMPAR: A new parallel benchmark for performance and energy consumption evaluationConcurrency and Computation: Practice and Experience10.1002/cpe.550432:20Online publication date: 3-Oct-2019
  • (2018)State access patterns in stream parallel computationsInternational Journal of High Performance Computing Applications10.1177/109434201769413432:6(807-818)Online publication date: 1-Nov-2018
  • (2018)Efficient NAS Benchmark Kernels with C++ Parallel Programming2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)10.1109/PDP2018.2018.00120(733-740)Online publication date: Mar-2018
  • (2017)Bringing Parallel Patterns Out of the CornerACM Transactions on Architecture and Code Optimization10.1145/313271014:4(1-26)Online publication date: 24-Oct-2017
  • (2017)Optimization Strategies for WRF Single-Moment 6-Class Microphysics Scheme (WSM6) on Intel Microarchitectures2017 Fifth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR.2017.58(146-152)Online publication date: Nov-2017

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