Concepts of the System/370 vector architecture

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Concepts of the System/370 vector architecture

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International Symposium on Computer Architecture archive
Proceedings of the 14th annual international symposium on Computer architecture table of contents

Pittsburgh, Pennsylvania, United States

Pages: 282 - 288

Year of Publication: 1987

ISBN:0-8186-0776-9

Authors

B. Moore	Data Systems Division, IBM Corporation, Poughkeepsie, NY
A. Padegs	Data Systems Division, IBM Corporation, Poughkeepsie, NY
R. Smith	Data Systems Division, IBM Corporation, Poughkeepsie, NY
W. Buchholz	Data Systems Division, IBM Corporation, Poughkeepsie, NY

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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ABSTRACT

This paper discusses the performance, complexity and system-integration considerations that shaped the System/370 Vector Architecture [1, 9]. The architecture is intended for compatible systems providing a range of price and performance. The paper reviews the reasons for choosing a register-oriented architecture with compound instructions over storage-to-storage operations and vector-instruction chaining. Then it discusses the role of cache in stride-N storage accessing, and describes some new facilities introduced for control-program purposes.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W. Buchholz, "The IBM System/370 Vector Architecture," IBM Systems J., vol. 25, pp. 51-62, June 1986.
	2	Cray X-MP Series Mainframe Reference Manual, HR-0032, Cray Research, Inc.
	3	T. Hirakuri, A. Tabata, T. Tsuchimoto, and S. Taguchi, "Super Computer FACOM VP in Parallel Pipeline Processing System Achieving a Machine Cycle of 7.5 ns" (in Japanese), Nikkei Electronics, vol. 314, pp. 131-155, April 11, 1982.
	4	T. Odaka, K. Kobayashi, T. Kawabe, and S. Nagashima, "Super Computer HITAC S-810 Featuring 630 MFLOPS (Max. Performance) and IG Byte Semiconductor Extended Storage" (in Japanese), Nikkei Electronics, vol. 314, pp. 159-184, April 11, 1982.
	5	K. Kokatsu, S. Watanabe, and R. Kondo, "The SX Supercomputer System with Max. Performance of 1.3 GFLOPS and 6 ns Machine Cycle Time" (in Japanese), Nikkei Electronics, Nov. 19, 1984.
	6	S. G. Tucker, "The IBM 3090 System - An Overview," IBM Systems J., vol. 25, pp. 4-19, June 1986.
	7	CDC Cyber 200 Model 205 Computer System, Hardware Reference Manual, No. 60256020, CDC.
	8	T. Cheung, R. M. Keller, and J. E. Smith, "An Analysis of the Cray X-MP Memory System," Proc. 1984 Int. Conf. Parallel Processing, pp. 499-505, Aug. 21-24, 1984.
	9	Andris Padegs , Brian B. Moore , Ronald M. Smith , Werner Buchholz, The IBM System/370 Vector Architecture: Design Considerations, IEEE Transactions on Computers, v.37 n.5, p.509-520, May 1988 [doi>10.1109/12.4602 ]
	10	IBM 3090 System Summary - Engineering/Scientific, No. 185-120, IBM.