- 1.S.M. ReAdy, M. K. ReAdy and V. D. Agrawal, "Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits", in Proc. Int. Syrup. on Fault-Tolerant Computing, Florida, pp. 44-49, June 1984.Google Scholar
- 2.G.L. Smith, "Model for delay faults based upon paths," in Proc. Int. Test Conf., pp. 342-349, Nov. 1985.Google Scholar
- 3.C.J. Lin and S. M. Reddy, "On delay fault testing in logic circuits," IEEE Trans. CAD, pp. 694-703, Sept. 1987.Google Scholar
- 4.E.S. Park and M. R. Mercer, "Robust and nonrobust tests for path delay faults in a combinational logic," in Proc. Int. Test Conf., pp. 1027-1034, Sept. 1987.Google Scholar
- 5.M.H. Schultz, F. Fink and K. Fuchs, "Parallel Pattern Fault Simulation of Path Delay Faults", in Pt'oc. Design Autom. Conf., pp. 357-363, June 1989. Google ScholarDigital Library
- 6.M.H. Schultz, K. Fuchs and F. Fink, "Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults", in Proc. Int. Symp. on Fault-Tolerant Computing, pp. 44-51, June 1989.Google Scholar
- 7.T.W. Williams, B. Underwood and M. R. Mercer, "The Interdependence between Delay-Optimization of Synthesized Networks and Testing", in Proc. 28th Design Automation Conf., June 1991, pp. 87-92. Google ScholarDigital Library
- 8.S. Even, Graph Algorithms, Computer Science Press, 1979. Google ScholarDigital Library
- 9.I. Pomeranz and S. M. ReAdy, "An Efficient Non- Enumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits", technical report No. 10-1-1991 Revised 7-11-1992, Electrical & Computer Eng. Dept., U. of Iowa.Google Scholar
- 10.i. Pomeranz, L. N. Reddy and S. M. ReAdy, "SPADES: A Simulator for Path Delay Faults in Sequential Circuits", to appear in EURO-DAC '92, Sept. 1992. Google ScholarDigital Library
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- An efficient non-enumerative method to estimate path delay fault coverage
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An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits
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On test coverage of path delay faults
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Line coverage of path delay faults
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