Peichen Pan
- 1.Chong, K. ~nd S. Sahni, Optimal Realizations o! Floorplans. TR 90-20, CS Dept, Univeisity of Minnesota, 1990.Google Scholar
- 2.Lengauer, T., Combinatorial Algorithms }or Integrated Circuit La!~out. John Wiley & Sons, New York, 1990. Google ScholarDigital Library
- 3.Liu, C. L., Introduction to Combinatorial Mathematics. McGraw-Hill Book Corap~ny, New York, 1968.Google Scholar
- 4.Otten, I:I.H.J.M., Graphs in Floorplan Design. Intl. Journal of Circuit Theory and Appl., Vol 16, 391-410, 1988.Google ScholarCross Ref
- 5.Pan, Peichen and C. L. Liu, Unpublished notes. 1991.Google Scholar
- 6.Part, Peichen and C. L. Liu, Manuscript. 1992.Google Scholar
- 7.Stockmeyer, L., Optimal Orientation.s o! Cells in Slicing FIoorplan Designs. Info. and Control, Vol 59, 91-101, 1983. Google ScholarDigital Library
- 8.Wang, T. and D.F. Wong, An Optimal Algorithm }or Floorplan .Area Optimization. Proc. 27th DAC, 180-186, 1990. Google ScholarDigital Library
- 9.Wimer, S., I. Koren, and I. Cederbaum, Optimal Aspect Ratios of Building Blocks in VLSI. IEEE ~rans. on CAD, V01 8, No 2,139-145, 1989.Google Scholar
- 10.Wong, D.F. and P.S. Sakhamm'i, Efficient Floorplan Area Optimization. Proc. 26th DAC, 586-589, 1989. Google ScholarDigital Library
Index Terms
- Area minimization for general floorplans
Recommendations
Area minimization for floorplans
In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two ...
Area minimization for hierarchical floorplans
In this paper we study the area-minimization problem for hierarchical floorplans. We settle an open problem on the complexity of the area-minimization problem for hierarchical floorplans by showing it to be NP-complete (even for balanced hierarchical ...
Slicing Floorplans with Handling Symmetry and General Placement Constraints
ISVLSI '14: Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSIFloorplan design is an essential step in physical design of VLSI circuits and its results directly determine the performance of the final packing. Existing floorplanners that use slicing floorplans are efficient in runtime and capable of getting a tight ...
Comments