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Adapting cache line size to application behavior

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Published:01 May 1999Publication History
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References

  1. 1.D. H. Albonesi, Dynamic IPC/Clock Rate Optimization, intl. $ymposmm on Computer Architecture, pp. 282-292, June 1998.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.A. Chien and J. Kim, Planar Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors, Intl. Symposium on Computer Architecture, pp. 268-277, July 1992.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3.W. J. Dally and H. Aoki, Deadlock-free adaptive routing in multicomputer networks using virtual channels, IEEE Transactions on Parallel and Distributed Systems, vol. 4, pp. 466-475, Apr 1993.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.Fredrik Dahlgren, Michel Dubois and Per Stenstrom, Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors, Intl. Conference on Parallel Processing, Aug, 1993.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.J. Kuskin et al, The Stanford FLASH Multiprocessor, Intl. Symposium on Computer Architecture, pp. 302-313, April 1994.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.Edward H. Cornish and Alex Veidenbaum, An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors, Intl. Conference on Parallel Processing, Aug. 1994.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.PentiumTM Processor User's Manual, Intel Corporation, 1993.]]Google ScholarGoogle Scholar
  8. 8.T. Juan, S. Sanjeevan, and J. Navaro, Dynamic History Length Fitting: a Third Level of Adaptivity for Branch Prediction, intl. Symposium on Computer Architecture, pp.155-166, July 1998.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.K. Inoue, K. Kai, and K. Marukami, High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs, Japanese IEICE Transactions on Electronics, Vol. E81-C No. 9, pp. 1438-1447, September 1999.]]Google ScholarGoogle Scholar
  10. 10.S. Kumar and C. Wilkerson, Exploiting Spatial Locality in Data Caches Using Spatial Footprints, Intl. Symposium on Computer Architecture,pp. 357-368, June 1998]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. 11.MIPS R3000 hardware manual, MIPS Corporation.]]Google ScholarGoogle Scholar
  12. 12.T. Matsumoto, K. Nishimura, T. Kudoh, K. Hiraki, H. Amano, and H. Tanaka, Distributed Shared Memory Architecture for JUMP-i: A General-Purpose MPP Prototype, Intl. Symposium on Parallel Architecures, Algorithms, and Networks, pp. 131-137, June 1996.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. 13.Steve Turner and Alex Veidenbaum, Scalability of the Cedar System, Supercomputing, pp. 247-254, 1994.]]Google ScholarGoogle Scholar
  14. 14.Jack E. Veenstra and Robert J. ~Fowler, MINT: A Front End for Efficient Simulation of Shared- Memory Multiprocessors, Intl. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems , pp. 201-207, Jan. 1994.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. 15.T.-Y. Yeh and Y. N. Patt, Two Level Adaptive Training Branch Prediction, Intl. Symposium on Microarchitecture, pp. 51-61, Nov. 1991.]] Google ScholarGoogle ScholarDigital LibraryDigital Library

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                      cover image ACM Conferences
                      ICS '99: Proceedings of the 13th international conference on Supercomputing
                      June 1999
                      509 pages
                      ISBN:158113164X
                      DOI:10.1145/305138

                      Copyright © 1999 ACM

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                      • Published: 1 May 1999

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                      ICS '99 Paper Acceptance Rate57of180submissions,32%Overall Acceptance Rate584of2,055submissions,28%

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