Fault tolerance design for NoCs: partial virtual-channel sharing

ABSTRACT

As the industry of Network of Chips (NoCs) evolves, the reliability and performance of these systems are becoming more critical requirement. The fault tolerance issue is an essential factor that has a direct impact on the reliability of the system. Many techniques were developed to boost the fault tolerance capability of NoCs. This is either implemented on the routing algorithm level or architecture level. This paper analyzes previous work that enhances the fault tolerance by modifying the router architecture. The model of Partial Virtual Sharing (PVS) architecture was modified to improve the fault tolerance capability. We proposed a technique to implement fault tolerance at the input unit of the router architecture. Additional enhancements to implement fault tolerance at the output unit of the router was proposed and implemented too. The reliability of the proposed design was evaluated and compared based on the Mean Time Between Failure (MTBF) metric. The proposed design had shown a remarkable improvement of 263.2% over existing approaches.

References

1. Lehtonen, T. 2009. On fault tolerance methods for networks-on-chip. Turku Centre for Computer Science (TUCS), Finland, TURKU.
2. Mahanta, H. J., Biswas, A., and Hussain, M. A. 2014. Networks on chip: The new trend of on-chip interconnection. In IEEE Fourth International Conference on Communication Systems and Network Technologies (CSNT), Bhopal, 1050--1053.
3. Latif, K., Rahmani, A. M., Nigussie, E., Tenhunen, H., and Seceleanu, T. 2011. A novel topology-independent router architecture to enhance reliability and performance of Networks-on-Chip. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, BC, 454--462.
4. Park, D., Nicopoulos, C., Kim, J., Vijaykrishnan, N., and Das, C. R. 2006. Exploring fault-tolerant network-on-chip architectures. In IEEE International Conference on Dependable Systems and Networks (DSN). Philadelphia, PA, 93--104.
5. Kang, Y. H., Kwon, T. J., and Draper, J. 2010. Fault-tolerant flow control in on-chip networks. In Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), Washington, DC, USA, 79--86.
6. Zhang, L., Du, H., and Han, J. 2008. ftNoC: A New Architecture of Network on Chip with Fault-Tolerance. In International Colloquium on Computing, Communication, Control, and Management (ISECS). Guangzhou, 193-- 197.
7. Chang, Y. C., Chiu, C. T., Lin, S. Y., and Liu, C. K. 2011. On the design and analysis of fault tolerant NoC architecture using spare routers. In Proceedings of the 16th Asia and South Pacific Design Automation Conference. Yokohama, 431--436.
8. DeOrio, A., Fick, D., Bertacco, V., Sylvester, D., Blaauw, D., Hu, J., and Chen, G. 2012. A reliable routing architecture and algorithm for NoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(5), 726--739.
9. Grecu, C., Anghel, L., Pande, P. P., Ivanov, A., and Saleh, R. 2007. Essential fault- tolerance metrics for NoC infrastructures. In 13th IEEE International On-Line Testing Symposium (IOLTS 07). Crete, 37--42.

Index Terms

• Computer systems organization

  • Dependable and fault-tolerant systems and networks

    • Reliability

• Hardware

  • Hardware test

    • Hardware reliability screening