ABSTRACT
The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and energy efficiency, and can potentially alleviate the memory wall problem. In this paper, we propose an optical inter/intra-chip processor-memory communication architecture, called MOCA. Experimental results and analysis show that MOCA can significantly improve system performance and energy efficiency. For example, comparing to Hybrid Memory Cube (HMC), MOCA can speedup application execution time by 2.6x, reduce communication latency by 75%, and improve energy efficiency by 3.4x for 256-core processors in 7 nm technology.
- A. N. Udipi et al., "Combining Memory and a Controller with Photonics Through 3D-stacking to Enable Scalable and Energy-efficient Systems," in ISCA, 2011. Google ScholarDigital Library
- A. Hadke et al., "Design and Evaluation of an Optical CPU-DRAM Interconnect," in ICCD, 2008.Google Scholar
- S. Beamer et al., "Re-architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics," in ISCA, 2010. Google ScholarDigital Library
- C. Batten et al., "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics," in HOTI, 2008. Google ScholarDigital Library
- D. Brunina et al., "An Energy-Efficient Optically Connected Memory Module for Hybrid Packet- and Circuit-Switched Optical Networks," JSTQE, vol. 19, March 2013.Google Scholar
- S. L. Beux et al., "Potential and Pitfalls of Silicon Photonics Computing and Interconnect," in ISCAS, 2013.Google Scholar
- W. Y. Tsai et al., "A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link," TCSI, vol. 59, pp. 2600--2610, Nov 2012.Google Scholar
- G. Kim et al., "Memory-centric System Interconnect Design with Hybrid Memory Cubes," in PACT, 2013. Google ScholarDigital Library
- T. Krishna et al., "Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip," in MICRO, 2014.Google Scholar
- "Hybrid Memory Cube Specification 2.0," Technical Publication, 2014.Google Scholar
- J. Zhan et al., "A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers," in MICRO, 2016.Google Scholar
- S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," in MICRO, 2009. Google ScholarDigital Library
- X. Wu et al., "An Inter/Intra-Chip Optical Network for Manycore Processors," TVLSI, vol. 23, pp. 678--691, April 2015.Google Scholar
- C. Schow et al., "A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single "Holey" CMOS IC," JLT, vol. 29, pp. 542--553, Feb 2011.Google Scholar
- R. K. V. Maeda et al., "JADE: A Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models," in AISTECS, 2016. Google ScholarDigital Library
- J. D. McCalpin, "Memory Bandwidth and Machine Balance in Current High Performance Computers," TCCA, pp. 19--25, Dec. 1995.Google Scholar
- P. Rosenfeld et al., "DRAMSim2: A Cycle Accurate Memory System Simulator," CAL, vol. 10, pp. 16--19, Jan 2011. Google ScholarDigital Library
- O. Naji et al., "A High-level DRAM Timing, Power and Area Exploration Tool," in SAMOS, 2015.Google Scholar
- O. Naji et al., "Calculating Memory System Power for DDR3," Technical Publication, 2014.Google Scholar
- Z. Wang et al., "Improve Chip Pin Performance Using Optical Interconnects," TVLSI, vol. 24, pp. 1574--1587, April 2016.Google Scholar
- "Corning® Single-Mode Optical Fiber," Technical Publication.Google Scholar
- Q. Xu et al., "Micrometre-scale Silicon Electro-optic Modulator," Nature, vol. 435, no. 7040, pp. 325--327, 2005.Google ScholarCross Ref
- Y. Zhang et al., "Towards Adaptively Tuned Silicon Microring Resonators for Optical Networks-on-Chip Applications," JSTQE, vol. 20, pp. 136--149, July 2014.Google Scholar
- A. Supalov et al., Optimizing HPC Applications with Intel Cluster Tools. Apress, 2014. Google ScholarDigital Library
Recommendations
MoCA: A Middleware for Developing Collaborative Applications for Mobile Users
The Mobile Collaboration Architecture is a middleware architecture for developing and deploying context-aware collaborative applications for mobile users. MoCA comprises client and server APIs, a set of core services for registering applications, the ...
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. ...
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip
Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated ...
Comments