Annette Reutter
- {BAMS98} J. Böttger, K. Agsteiner, D. Monjau, S. Schulze: An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse. Proceedings of DATE in Paris, 1998. Google Scholar
Digital Library
- {Bake98} S. Baker: Virtual Socket Interface AllianceTM. Designer Track, DATE in Paris, 1998.Google Scholar
- {BeBS98} B. Behnam, K. Babba, G. Saucier: IP Taxonomy, IP Searching in a Catalog. Designer Track, DATE in Paris, 1998.Google Scholar
- {FaSe98} N. Faulhaber, R. Seepold: An Efficient Similarity Metric for IP Reuse in RMS. Proceedings of 2. Workshop "Reuse Techniques for VLSI Design" in Karlsruhe, 1998.Google Scholar
- {GKRR98} D. Garte, T. Kunjan, A. Reutter, S. Riedel, S. Rülke: Survey on a Practicable "Design for Reuse" Strategy Including Design Flow and Testbench Aspects. Proceedings of 2. Workshop "Reuse Techniques for VLSI Design" in Karlsruhe, 1998.Google Scholar
- {HaKn98} S. Hauck, S. Knol: Data Security for Web-based CAD. Proceedings of DAC in San Francisco, 1998. Google ScholarDigital Library
- {JDKR97} A. A. Jerraya, H. Ding, P. Kission, M. Rahmouni: Behavioral Synthesis and Component Reuse with VHDL. Kluwer Academic Publishers, Boston/Dordrecht/London, 1997. Google ScholarDigital Library
- {KCGW98} M. Koegst, P. Conradi, D. Garte, M. Wahl: A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits. Proceedings of DATE in Paris, 1998. Google ScholarDigital Library
- {KeBr98} M. Keating, P. Bricaud: Reuse Methodology Manual. Kluwer Academic Publishers, Boston/Dordrecht/ London, 1998.Google Scholar
- {LeWM98} G. Lehmann, B. Wunder, K.D. Müller-Glaser: A VHDL Reuse Workbench. Proceedings of EURODAC in Geneva, 1996. Google ScholarDigital Library
- {OAIP98} S. Olcoz, L. Ayuda, I. Izaguirre, O. Penalba: VHDL Teamwork, Organization Units and Workspace Management. Proceedings of DATE in Paris, 1998. Google ScholarDigital Library
- {PHSM95} V. Preis, R. Henftling, M. Schütz, S. März-Rössel: A Reuse Scenario for the VHDL-Based Hardware Design Flow. Proceedings of EURO-DAC in Brighton, 1995. Google ScholarDigital Library
- {RMKR97} A. Reutter, B. Mößner, I. Kreuzer, W. Rosenstiel: Wiederverwendung komplexer Komponenten für Synthese und Simulation unter Verwendung von VHDL. Proceedings of 8. E.I.S.-Workshop in Hamburg, April 1997.Google Scholar
- {ReMR98a} A. Reutter, B. Mößner, W. Rosenstiel: Design of generic components for efficient reuse in high level designs. Proceedings of SDA-Workshop in Dresden, 1998.Google Scholar
- {ReMR98b} A. Reutter, B. Mößner, W. Rosenstiel: Design of reusable modules for high level designs. Proceedings of International Workshop on IP Based Synthesis and Simulation in Grenoble, 1998.Google Scholar
- {VSIA97} "Virtual SocketTM Interface Architecture Document", Virtual Socket Interface Alliance, 1997, http:/ /www.vsi.org/library/vsi-or.pdfGoogle Scholar
Index Terms
- An efficient reuse system for digital circuit design
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