An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect

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An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th ACM/IEEE conference on Design automation table of contents

New Orleans, Louisiana, United States

Pages: 1 - 6

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Jing-Rebecca Li	Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
Frank Wang	Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
Jacob K. White	Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 24, Citation Count: 12

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 12

	L. Miguel Silveira , Joel R. Phillips, Exploiting input information in a model reduction algorithm for massively coupled parasitic networks, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Jing-Rebecca Li , Jacob White, Efficient model reduction of interconnect via approximate system gramians, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.380-384, November 07-11, 1999, San Jose, California, United States
	Payam Heydari , Massoud Pedram, Balanced truncation with spectral shaping for RLC interconnects, Proceedings of the 2001 conference on Asia South Pacific design automation, p.203-208, January 2001, Yokohama, Japan
	Joel Phillips , L. Miguel Silveira, Poor Man's TBR: A Simple Model Reduction Scheme, Proceedings of the conference on Design, automation and test in Europe, p.20938, February 16-20, 2004
	Payam Heydari , Massoud Pedram, Model reduction of variable-geometry interconnects using variational spectrally-weighted balanced truncation, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Xuan Zeng , Dian Zhou , Wei Cai, An efficient DC-gain matched balanced truncation realization for VLSI Interconnect circuit order reduction, Microelectronic Engineering, v.60 n.1, p.3-15, January 2002
	J. R. Phillips, Variational interconnect analysis via PMTBR, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.872-879, November 07-11, 2004
	Q. Su , V. Balakrishnan , C-K. Koh, Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.311, January 07-11, 2002
	Q. Su , V. Balakrishnan , C.-K. Koh, A factorization-based framework for passivity-preserving model reduction of RLC systems, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Chandramouli V. Kashyap , Byron L. Krauter, A realizable driving point model for on-chip interconnect with inductance, Proceedings of the 37th conference on Design automation, p.190-195, June 05-09, 2000, Los Angeles, California, United States
	Joel R. Phillips, Projection frameworks for model reduction of weakly nonlinear systems, Proceedings of the 37th conference on Design automation, p.184-189, June 05-09, 2000, Los Angeles, California, United States
	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States