Gate-level design exploiting dual supply voltages for power-driven applications

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Gate-level design exploiting dual supply voltages for power-driven applications

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th ACM/IEEE conference on Design automation table of contents

New Orleans, Louisiana, United States

Pages: 68 - 71

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Chingwei Yeh	EE & Nat'l Chung-Cheng Univ., Chiayi 621, Taiwan, ROC
Min-Cheng Chang	CS, Nat'l Chung-Cheng Univ., Chiayi 621, Taiwan, ROC
Shih-Chieh Chang
Wen-Bone Jone	CS, Nat'l Chung-Cheng Univ., Chiayi 621, Taiwan, ROC

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 7

Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. P. Chandrakasan and R. W. Brodersen, Low-power CMOS digital design, Kluwer Academic Publishers, 1995.
	2	T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Algorithms, Chap. 27, MIT Press, McGraw-Hill Book Co., 1992.
	3	Dimitrios Kagaris , Spyros Tragoudas, Maximum independent sets on transitive graphs and their applications in testing and CAD, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.736-740, November 09-13, 1997, San Jose, California, United States
	4	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224084]
	5	J. D. Meindl, "Low power microelectronics: retrospect and prospect," Proc. IEEE, vol. 83, no. 4, Apr. 1995.
	6	E. M. Sentovich et al, "SIS : A System for Sequential Circuit Synthesis," Technical report UCB/ERL M92/41, Univ. of California, Berkeley, May 1992.
	7	D. Singh et al., "Power conscious CAD tools and methodologies: a perspective," Proc. IEEE, vol. 83, no. 4, Apr. 1995, pp. 570-593.
	8	Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]
	9	K. Usami et al., "Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor" IEEE J. Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 463-472.
	10	Wang, J. S., Shieh, S. J., Wang, J. C., and Yeh, C. Design of standard cells used in low power ASICs exploiting multiplesupply-voltage scheme. Proc. 11 th ASIC Conf., Sept. 1998.

CITED BY 7

	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik, Evaluation of dual V_DD fabrics for low power FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Sarvesh H. Kulkarni , Dennis Sylvester, Power distribution techniques for dual VDD circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Bipul C. Paul , Amit Agarwal , Kaushik Roy, Low-power design techniques for scaled technologies, Integration, the VLSI Journal, v.39 n.2, p.64-89, March 2006