Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. E Chandrakasan and R. W. Brodersen, "Low Power CMOS Digital Design" IEEE Journal of Solid State Circuits, vol. 27, pp. 473-484, April. 1992.
	2	S. Mutoh et al., "I-V Power Supply High-Speed Digital Circuits Technology with Multithreshold-voltage CMOS," IEEE Journal of Solid State Circuits, vol. 30, pp. 847-854, Aug. 1995.
	3	T. Kuroda et al., "A High-Speed Low-Power 0.3 mm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme" in Proc. IEEE Custom Integrated Circuits Conference, pp. 53-56, May 1996.
	4	Mutsunori Igarashi , Kimiyoshi Usami , Kazutaka Nogami , Fumihiro Minami , Yukio Kawasaki , Takahiro Aoki , Midori Takano , Chiharo Mizuno , Takashi Ishikawa , Masahiro Kanazawa , Shinji Sonoda , Makoto Ichida , Naoyuki Hatanaka, A low-power design method using multiple supply voltages, Proceedings of the 1997 international symposium on Low power electronics and design, p.36-41, August 18-20, 1997, Monterey, California, United States  [doi>10.1145/263272.263279]
	5	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States  [doi>10.1145/224081.224084]
	6	Mark C. Johnson , Kaushik Roy, Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors, p.72-77, October 07-09, 1996
	7	Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997  [doi>10.1109/92.645070 ]
	8	W. Shiue and C. Chakrabarthi, "Low Power Scheduling with Resources at Multiple Voltages" in Proceedings oflSCAS-98, (Monterey, CA, USA), June 1998.

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