- 1.M. Keaton, P. Bricaud, Reuse Methodology Manual For System- On-A-Chip Designs, Kluwer Academic Publishers, 1998. Google ScholarDigital Library
- 2.TI's 0.07 Micron CMOS Technology Ushers In Era of Gigahertz DSP and Analog Performance, Texas Instruments, Published in the Internet, http://www.ti.com/sc/docs/news/1998/98079.htm, 1998.Google Scholar
- 3.R.K. Gupta, Y. Zorian, Introducing Core-Based System Design, IEEE Design & Test of Computers Magazine, Vol. 13, No. 4, pp. 15- 25. 1997. Google ScholarDigital Library
- 4.F. Vahid, D.D. Gajski, J. Gong, A Binary-Constraint Search Algorithm for Minimizing Hardware during Hardware~Software Partitioning, IEEE/ACM Proc. of The European Conference on Design Automation (EuroDAC) 1994, pp. 214-219, 1994. Google ScholarDigital Library
- 5.R.K. Gupta and G.D. Micheli, System-level Synthesis using Reprogrammable Components, IEEE/ACM Proc. of EDAC'92, IEEE Comp. Soc. Press, pp. 2-7, 1992.Google ScholarCross Ref
- 6.Z. Peng, K. Kuchcinski, An Algorithm for Partitioning of Application Specific System, IEEE/ACM Proc. of The European Conference on Design Automation (EuroDAC) 1993, pp. 316-321, 1993.Google ScholarCross Ref
- 7.J. Madsen, P. V. Knudsen, LYCOS Tutorial, Handouts from Eurochip course on Hardware/Software Codesign, Denmark, 14.-18. Aug. 1995.Google Scholar
- 8.T. Y. Yen, W. Wolf, Multiple-Process Behavioral Synthesis for Mixed Hardware-Software Systems, IEEE/ACM Proc. of 8th. International Symposium on System Synthesis, pp. 4-9, 1995. Google ScholarDigital Library
- 9.A. Kalavade, E. Lee, A Global Critically~Local Phase Driven Algorithm for the Constraint Hardware~Software Partitioning Problem, Proc. of 3rd. IEEE Int. Workshop on Hardware/Software Codesign, pp. 42-48, 1994. Google ScholarDigital Library
- 10.I. Hong, D. Kirovski et al., Power Optimization of Variable Voltage Core-Based Systems, IEEE Proc. of 35th. Design Automation Conference (DAC98), pp.176-181, 1998. Google ScholarDigital Library
- 11.B.P. Dave, G. Lakshminarayana, N.K. Jha, COSYN. Hardware- Software Co-Synthesis of Embedded Systems' IEEE Proc. of 34th. Design Automation Conference (DAC97), pp.703-708, 1997. Google ScholarDigital Library
- 12.V. Tiwari, S. Malik, A. Wolfe, Instruction Level Power Analysis and Optimization of Software, Kluwer Academic Publishers, Journal of VLSI Signal Processing, pp. 1-18, 1996. Google ScholarDigital Library
- 13.Ch.Ta Hsieh, M. Pedram, G. Mehta, F.Rastgar, Profile-Driven Program Synthesis for Evaluation of System Power Dissipation, IEEE Proc. of 34th. Design Automation Conference (DAC97), pp.576- 581, 1997. Google ScholarDigital Library
- 14.P.-W. Ong, R.-H. Ynn, Power-Conscious Software Design - a framework for modeling software on hardware, IEEE Proc. of Symposium on Low Power Electronics, pp. 36-37, 1994.Google Scholar
- 15.T. Sato, M. Nagamatsu, H. Tago, Power and Performance Simulator: ESP and its Application for 1 O0 MIPS/W Class RISC Design, IEEE Proc. of Symposium on Low Power Electronics, pp. 46-47, 1994.Google Scholar
- 16.A.W. Aho, R. Sethi and J.D. Ullmann, COMPILERS Principles, Techniques and Tools, Bell Telephone Laboratories, 1987. Google ScholarDigital Library
- 17.M.D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS: Wisconsin Architectural Research Tool Set, Computer Science Department University of Wiscocnsin.Google Scholar
- 18.P. Landman and J. Rabaey, Architectural Power Analysis: The Dual Bit Type Method, IEEE Transactions on VLSI Systems, Vol.3, No.2, June 1995. Google ScholarDigital Library
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A low power hardware/software partitioning approach for core-based embedded systems
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