research-article

FPGA based ASIC Emulator with High Speed Optical Serial Links

Authors:

Toshinori SueyoshiAuthors Info & Claims

HEART '17: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

Article No.: 18, Pages 1 - 6

https://doi.org/10.1145/3120895.3120913

Published: 07 June 2017 Publication History

Get Access

Abstract

We propose a multiple FPGA system using high speed optical serial interface built in recent FPGAs and construct ASIC emulator. Although conventional system which uses parallel connection is limited to bandwidth of the number of I/Os, proposed system has no restriction. In this paper, we implement the circuit using Kintex Ultrascale which has optical high speed serial interface and evaluate its performance using five VTR benchmark circuits. As a result, we found that proposed system operated at 21.3MHz. Furthermore, if we use a Virtex Ultrascale+, operating frequency increases up to 29.97MHz.

References

[1]

K.Fleming ĄCM.Adler ĄCM.Pellauer ĄCA.Parashar ĄCArvind ĄCJ.Emer, "Leveraging Latency-Insensitivity to Ease Multiple FPGA," Proc. FPGA, pp 175--184, Feb. 2012.

Google Scholar

[2]

WJ.Fang ĄCA.C.-H. Wu, "A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations," Proc. ICCAD, pp 638--643, Oct. 1996.

Google Scholar

[3]

M.Butts, Logic Emulation and Prototyping, "It's the Interconnect (Rent rules)," RAMP Wrap, Aug 2010.

Google Scholar

[4]

K.Takahashi, M.Amagasaki, M.Kuga, M.Iida, T.Sueyoshi, "Circuit Partitioning Methods for FPGA-based ASIC Emulator using High-speed Serial Wires", Proc. SASIMI, pp. 317--318, Mar. 2012.

Google Scholar

[5]

Mario P. VestiasĄCHoracio C. Neto, "Area and performance optimization of a generic network-on-chip architecture," Proc. SBCCI, pp. 68--73, Aug. 2006.

Google Scholar

[6]

H.Nakajo, K.Matsuda, T.Miyoshi, M.Takemoto, S.Funada: "A verification method of a partitioned circuit with a high level synthesis tool based on java language.", Proc. ACOMP, pp. 1--9, Nov. 2014.

Google Scholar

[7]

T.Kajiwara, Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi, "A Novel Three-dimensional FPGA Architecture with High-speed Serial Communication Links," Proc. ICFPT, pp. 306--309, Dec. 2014.

Crossref

Google Scholar

[8]

University of Minnesota ĄCG.Karypis, "METIS 5.1.x Manual," Mar. 2013.

Google Scholar

[9]

KC.Nunna ĄCF.Mehdipour ĄCK.Murakami, "3D FPGA versus multiple FPGA system: enhanced parallelism in smaller area," Proc. AusPDC, Vol. 152, pp. 37--43, Jan.2014.

Google Scholar

Cited By

View all

Tie JPan GDeng LXun CLuo LZhou L(2024)A Method of Extracting and Visualizing Hierarchical Structure of Hardware Logic Based on Tree-Structure For FPGA-Based Prototyping2024 9th International Symposium on Computer and Information Processing Technology (ISCIPT)10.1109/ISCIPT61983.2024.10673222(554-561)Online publication date: 24-May-2024
https://doi.org/10.1109/ISCIPT61983.2024.10673222

Index Terms

FPGA based ASIC Emulator with High Speed Optical Serial Links
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

Recommendations

Implementing high-performance, low-power FPGA-based optical flow accelerators in C
ASAP '13: Proceedings of the 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Recent developments in High-Level Synthesis (HLS) for FPGAs are making it possible to “run” C code on FPGAs thereby making modern programming environments available to FPGA developers. In this paper, C code for a complex optical-flow algorithm is ...
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which ...
Design and evaluation of a hardware/software FPGA-based system for fast image processing

We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host ...

Comments

Information & Contributors

Information

Published In

HEART '17: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

June 2017

172 pages

ISBN:9781450353168

DOI:10.1145/3120895

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

Ruhr-Universität Bochum: Ruhr-Universität Bochum

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

HEART2017

HEART2017: The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

June 7 - 9, 2017

Bochum, Germany

Acceptance Rates

Overall Acceptance Rate 22 of 50 submissions, 44%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
66
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 09 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tie JPan GDeng LXun CLuo LZhou L(2024)A Method of Extracting and Visualizing Hierarchical Structure of Hardware Logic Based on Tree-Structure For FPGA-Based Prototyping2024 9th International Symposium on Computer and Information Processing Technology (ISCIPT)10.1109/ISCIPT61983.2024.10673222(554-561)Online publication date: 24-May-2024
https://doi.org/10.1109/ISCIPT61983.2024.10673222

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Implementing high-performance, low-power FPGA-based optical flow accelerators in C

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Design and evaluation of a hardware/software FPGA-based system for fast image processing

Comments

Information

Published In

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations