ABSTRACT
As the complexity of multi-core embedded systems continuously grows, the optimization and verification of such systems become non-trivial. Thus, it is important to secure a set of benchmarks of reasonable complexity to validate the design of multi-core embedded systems. Dataflow model has long been considered as a suitable model-of-computation for specifying the behavior of embedded systems. In this paper, we proposes a dataflow benchmark generation technique for multi-core embedded systems, leveraging two existing tools: a random dataflow topology generator and a random C code generator. In the proposed technique, as a preparatory step, a C code database is established by means of a random C code generation tool. Then, a random dataflow graph, with execution time information annotated to each node, is generated by an existing tool. For each node in the generated graph, a number of randomly generated C code segments are properly chosen and accommodated in a single function as per the given execution time information. In doing so, a set of linear equations are derived and solved. Subsequently, using existing model-based embedded system design frameworks, we automatically generate an executable benchmark for the entire dataflow graph. Further, in order to enhance the accuracy of the generated code, a simple calibration technique is applied after the generation and test runs. It is shown that the generated codes assure the diversity and complexity as embedded software benchmark for multi-core embedded systems.
- Robert P Dick, David L Rhodes, and Wayne Wolf. 1998. TGFF: task graphs for free. In Proceedings of the 6th international workshop on Hardware/software codesign. IEEE Computer Society, 97--101. Google ScholarDigital Library
- Sander Stuijk, Marc Geilen, and Twan Basten. 2006. SDF*** 3: SDF for free. In Application of Concurrency to System Design, 2006. ACSD 2006. Sixth International Conference on. IEEE, 276--278. Google ScholarDigital Library
- Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. In Computer Architecture, 1995. Proceedings., 22nd Annual International Symposium on. IEEE, 24--36. Google ScholarDigital Library
- Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques. ACM, 72--81. Google ScholarDigital Library
- Amit Kumar Singh, Muhammad Shafique, Akash Kumar, and Jörg Henkel. 2013. Mapping on multi/many-core systems: survey of current and emerging trends. In Proceedings of the 50th Annual Design Automation Conference. ACM, 1. Google ScholarDigital Library
- Edward A Lee and David G Messerschmitt. 1987. Synchronous data flow. Proc. IEEE 75, 9 (1987), 1235--1245.Google ScholarCross Ref
- KAHN Gilles. 1974. The semantics of a simple language for parallel programming. In Information Processing 74 (1974), 471--475.Google Scholar
- Kaivalya M Dixit. 1991. The SPEC benchmarks. Parallel computing 17, 10--11 (1991), 1195--1209. Google ScholarDigital Library
- SPEC CPU2006. 2006. Standard Performance Evaluation Corporation. (2006).Google Scholar
- Matthew R Guthaus, Jeffrey S Ringenberg, Dan Ernst, Todd M Austin, Trevor Mudge, and Richard B Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on. IEEE, 3--14. Google ScholarDigital Library
- Jason A Poovey, Thomas M Conte, Markus Levy, and Shay Gal-On. 2009. A benchmark characterization of the EEMBC benchmark suite. IEEE micro 29, 5 (2009). Google ScholarDigital Library
- Amir Hossein Ghamarian, Sander Stuijk, Twan Basten, MCW Geilen, and Bart D Theelen. 2007. Latency minimization for synchronous data flow graphs. In Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on. IEEE, 189--196. Google ScholarDigital Library
- Sander Stuijk, Twan Basten, MCW Geilen, and Henk Corporaal. 2007. Multi-processor resource allocation for throughput-constrained synchronous dataflow graphs. In Proceedings of the 44th annual Design Automation Conference. ACM, 777--782. Google ScholarDigital Library
- Lothar Thiele and Nikolay Stoimenov. 2009. Modular performance analysis of cyclic dataflow graphs. In Proceedings of the seventh ACM international conference on Embedded software. ACM, 127--136. Google ScholarDigital Library
- Shuvra S Bhattacharyya, Praveen K Murthy, and Edward A Lee. 1999. Synthesis of embedded software from synchronous dataflow specifications. The Journal of VLSI Signal Processing 21, 2 (1999), 151--166. Google ScholarDigital Library
- Harold J Curnow and Brian A Wichmann. 1976. A synthetic benchmark. Comput. J. 19, 1 (1976), 43--49.Google ScholarCross Ref
- Reinhold P Weicker. 1984. Dhrystone: a synthetic systems programming benchmark. Commun. ACM 27, 10 (1984), 1013--1030. Google ScholarDigital Library
- Shuai Che, Michael Boyer, Jiayuan Meng, David Tarjan, Jeremy W Sheaffer, Sang-Ha Lee, and Kevin Skadron. 2009. Rodinia: A benchmark suite for heterogeneous computing. In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on. Ieee, 44--54. Google ScholarDigital Library
- Xuejun Yang, Yang Chen, Eric Eide, and John Regehr. 2011. Finding and understanding bugs in C compilers. In ACM SIGPLAN Notices, Vol. 46. ACM, 283--294. Google ScholarDigital Library
- Yorick De Bock, Sebastian Altmeyer, Jan Broeckhove, and Peter Hellinckx. 2016. Task-Set Generator for Schedulability Analysis using the TACLeBench benchmark suite.. In EWiLi.Google Scholar
- Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, and Lothar Thiele. 2012. Scenario-based design flow for mapping streaming applications onto on-chip many-core systems. In Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems. ACM, 71--80. Google ScholarDigital Library
- Hanwoong Jung, Chanhee Lee, Shin-Haeng Kang, Sungchan Kim, Hyunok Oh, and Soonhoi Ha. 2014. Dynamic behavior specification and dynamic mapping for real-time embedded systems: Hopes approach. ACM Transactions on Embedded Computing Systems (TECS) 13, 4s (2014), 135. Google ScholarDigital Library
Index Terms
- Executable dataflow benchmark generation technique for multi-core embedded systems
Recommendations
Performance Gaps between OpenMP and OpenCL for Multi-core CPUs
ICPPW '12: Proceedings of the 2012 41st International Conference on Parallel Processing WorkshopsOpenCL and OpenMP are the most commonly used programming models for multi-core processors. They are also fundamentally different in their approach to parallelization. In this paper, we focus on comparing the performance of OpenCL and OpenMP. We select ...
Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling
SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded SystemsApplication modeling using dynamic dataflow graphs is well-suited for multi-core platforms. However, there is often a mismatch between the fine granularity of the application and the platform. Tailoring this granularity to the platform promises ...
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems
Special Issue on Innovations in Systems for Irregular Applications, Part 2Sparse matrix-vector multiplication (SpMV) operations are commonly used in various scientific and engineering applications. The performance of the SpMV operation often depends on exploiting regularity patterns in the matrix. Various representations and ...
Comments