Retractile clock-powered logic

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Retractile clock-powered logic

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 18 - 23

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Nestoras Tzartzanis	University of Southern California - Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, California
William Athas	University of Southern California - Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	William C. Athas , Lars J. Svensson , Jeffrey G. Koller , Nestoras Tzartzanis , Eric Ying-Chin Chou, Low-power digital systems based on adiabatic-switching principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.398-407, Dec. 1994 [doi>10.1109/92.335009 ]
	2	W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, A Low-Power Microprocessor Based on Resonant Energy, IEEE Jnl. of Solid-State Circuits, vol. 32, pp. 1693- 1701, Nov. 1997.
	3	W.C. Athas, L."J." Svensson, N. Tzartzanis, A Resonant Signal Driver For Two-Phase, Almost-Non-Overlapping Clocks, Proc. of the 1996 International Symposium on Circuits and Systems, Atlanta, GA, May 12-15, 1996.
	4	L."J." Svensson, J.G. Koller, Driving a Capacitive Load without Dissipating fCV2, Proc. of the 1994 Symposium on Low Power Electronics, pp. 100-101, San Diego, CA, Oct. 10-11, 1994.
	5	S.G. Younis, T.F. Knight, Asymptotically Zero Energy Split-Level Charge Recovery Logic, Proc. of the 1994 International Workshop on Low-Power Design, pp. 177- 182, Napa Valley, CA, Apr. 24-27, 1994.
	6	N. Tzartzanis, W. Athas, Clock-Powered Logic for a 50 MHz Low-Power Datapath, in iSSCC Digest of Technical Papers, pp. 338-339, San Francisco, CA, Feb. 6-8, 1997.
	7	S. Hall, An Electroid Switching Model for Reversible Computer Architectures, Proc. of the 1992 Workshop on Physics and Computation, PhysComp'92, Dallas, TX, Oct. 2-4, 1992.
	8	Lance A. Glasser , Daniel W. Dobberpuhl, The design and analysis of VLSI circuits, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985