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Selective instruction compression for memory energy reduction in embedded systems
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents
San Diego, California, United States
Pages: 206 - 211  
Year of Publication: 1999
ISBN:1-58113-133-X
Authors
Luca Benini  Universitià di Bologna, Bologna, Italy 40136
Alberto Macii  Politecnico di Torino, Torino, Italy 10129
Enrico Macii
Massimo Poncino  Politecnico di Torino, Torino, Italy 10129
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 37,   Citation Count: 29
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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4
Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
 
5
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6
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7
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16
Luca Benini , Giovanni de Micheli , Alberto Macii , Enrico Macii , Massimo Poncino, Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding, Proceedings of the Great Lakes Symposium on VLSI '98, p.8, February 19-24, 1998
 
17
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CITED BY  29
 
Yuan Xie , Wayne Wolf , Haris Lekatsas, Profile-Driven Selective Code Compression, Proceedings of the conference on Design, Automation and Test in Europe, p.10462, March 03-07, 2003
Haris Lekatsas , Jörg Henkel , Srimat Chakradhar , Venkata Jakkula , Murugan Sankaradass, CoCo: a hardware/software platform for rapid prototyping of code compression technologies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
Haris Lekatsas , Jörg Henkel , Venkata Jakkula, Design of an one-cycle decompression hardware for performance increase in embedded systems, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
 
Aviral Shrivastava , Nikil Dutt, Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA), Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.475-477, January 27-30, 2004, Yokohama, Japan
Alex K. Jones , Raymond Hoare , Dara Kusic , Gayatri Mehta , Josh Fazekas , John Foster, Reducing power while increasing performance with supercisc, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.3, p.658-686, August 2006
Susan Cotterell , Frank Vahid, Synthesis of customized loop caches for core-based embedded systems, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.655-662, November 10-14, 2002, San Jose, California
Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt, Energy-efficient instruction set synthesis for application-specific processors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
Luca Benini , Alberto Macii , Alberto Nannarelli, Cached-code compression for energy minimization in embedded processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.322-327, August 2001, Huntington Beach, California, United States
Susan Cotterell , Frank Vahid, Tuning of loop cache architectures to programs in embedded system design, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
 
O. Ozturk , H. Saputra , M. Kandemir , I. Kolcu, Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.882-887, March 07-11, 2005
 
Luca Benini , Francesco Menichelli , Mauro Olivieri, A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems, IEEE Transactions on Computers, v.53 n.4, p.467-482, April 2004
 
Peter Petrov , Alex Orailoglu, Low-power instruction bus encoding for embedded processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.8, p.812-826, August 2004
 
Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input Space Adaptive Embedded Software Synthesis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.711, January 07-11, 2002
 
Allen C. Cheng , Gary S. Tyson, An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs, IEEE Transactions on Computers, v.54 n.6, p.698-713, June 2005
Luca Benini , Alberto Macii , Massimo Poncino, Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.1, p.5-32, February 2003
Heidi Pan , Krste Asanović, Heads and tails: a variable-length instruction format supporting parallel fetch and decode, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
Frank Bellosa, The benefits of event: driven energy accounting in power-sensitive systems, Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system, September 17-20, 2000, Kolding, Denmark
Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression for low power embedded system design, Proceedings of the 37th conference on Design automation, p.294-299, June 05-09, 2000, Los Angeles, California, United States
Árpád Beszédes , Rudolf Ferenc , Tibor Gyimóthy , André Dolenc , Konsta Karsisto, Survey of code-size reduction methods, ACM Computing Surveys (CSUR), v.35 n.3, p.223-267, September 2003
 
Mihir Choudhury , Kyle Ringgenberg , Scott Rixner , Kartik Mohanram, Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Tohru Ishihara , Hiroto Yasuura, A power reduction technique with object code merging for application specific embedded processors, Proceedings of the conference on Design, automation and test in Europe, p.617-623, March 27-30, 2000, Paris, France
 
Alberto Macii , Enrico Macii , Fabrizio Crudo , Roberto Zafalon, A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors, Proceedings of the conference on Design, Automation and Test in Europe, p.10024, March 03-07, 2003
 
Chang Hong Lin , Yuan Xie , Wayne Wolf, Code compression for VLIW embedded systems using a self-generating table, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.10, p.1160-1171, October 2007
 
A. C. Cheng , G. S. Tyson, High-quality ISA synthesis for low-power cache designs in embedded microprocessors, IBM Journal of Research and Development, v.50 n.2/3, p.299-309, March 2006
Haris Lekatsas , Jörg Henkel , Wayne Wolf, Design and simulation of a pipelined decompression architecture for embedded systems, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
 
Jörg Henkel , Yanbing Li, Avalanche: an environment for design space exploration and optimization of low-power embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.454-468, August 2002
 
Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Henk Corporaal , Francky Catthoor, Instruction buffering exploration for low energy embedded processors, Journal of Embedded Computing, v.1 n.3, p.341-351, August 2005
Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression as a variable in hardware/software co-design, Proceedings of the eighth international workshop on Hardware/software codesign, p.120-124, May 2000, San Diego, California, United States
 
Murali Jayapala , Francisco Barat , Tom Vander Aa , Francky Catthoor , Henk Corporaal , Geert Deconinck, Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors, IEEE Transactions on Computers, v.54 n.6, p.672-683, June 2005

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

  E. Data
  E.4 CODING AND INFORMATION THEORY
      Subjects: Data compaction and compression

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics


General Terms:
Design, Measurement, Performance, Theory

Collaborative Colleagues:
Luca Benini: colleagues
Alberto Macii: colleagues
Enrico Macii: colleagues
Massimo Poncino: colleagues

Peer to Peer - Readers of this Article have also read:

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